hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 91

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

Table 44
Parameter
Self-Refresh Current
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are
floating, Data bus inputs are floating.
Operating Bank Interleave Read Current
1. All banks interleaving reads,
2. Timing pattern:
1)
2)
3)
4) Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS.
5) Definitions for
6) Timing parameter minimum and maximum values for
7) A = Activate, RA = Read with Auto-Precharge, D=DESELECT
Table 45
Parameter
LOW
HIGH
STABLE
FLOATING
SWITCHING
Data Sheet
t
commands. Address bus inputs are stable during deselects; Data bus is switching.
DDR2-400-333: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D (11 clocks)
DDR2-533-333: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D (15 clocks)
DDR2-533-444: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D (16 clocks)
DDR2-667-444: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks)
DDR2-667-555: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D (20 clocks)
V
I
I
CK
DD
DD
DDQ
specifications are tested after the device is properly initialized.
parameter are specified with ODT disabled.
=
= 1.8 V ± 0.1 V;
t
CK(IDD)
I
Definition for
DD
,
Measurement Conditions
I
t
Description
defined as
defined as
defined as inputs are stable at a HIGH or LOW level
defined as inputs are
defined as: Inputs are changing between high and low every other clock (once per two clocks)
for address and control signals, and inputs changing between high and low every other clock
(once per clock) for DQ signals not including mask or strobes
DD
RC
: see
=
t
RC(IDD)
V
Table 45
DD
= 1.8 V ± 0.1 V
I
V
V
DD
,
IN
IN
t
RRD
≤
≥
I
OUT
V
V
=
IL(ac).MAX
IH(ac).MIN
= 0 mA; BL = 4, CL = CL
t
RRD(IDD)
V
REF
=
; CKE is HIGH, CS is HIGH between valid
V
DDQ
/ 2
I
DD
Currents Measurement Specifications and Conditions
current measurements are defined in chapter 7..
92
(IDD)
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
, AL =
t
RCD(IDD)
-1 ×
512-Mbit DDR2 SDRAM
t
CK(IDD)
09112003-SDM9-IQ3P
;
Symbol Notes
I
I
DD6
DD7
Rev. 1.6, 2005-08
1)2)3)4)5)6)
1)2)3)4)5)6)7)