hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 41

no-image

hyb18t512160afl-3.7

Manufacturer Part Number
hyb18t512160afl-3.7
Description
512-mbit Ddr2 Sdram
Manufacturer
Infineon Technologies Corporation
Datasheet
Figure 14
Note: Asynchronous ODT timings apply for Precharge Power-Down Mode and “Slow Exit” Active Power Down
ODT timing mode switch
When entering the Power Down Modes “Slow Exit” Active Power Down and Precharge Power Down two additional
timing parameters (
Mode entry
As long as the timing parameter
when ODT is turned on or off before entering these
power-down modes, synchronous timing parameters
Data Sheet
CKE
ODT
CK, CK
DQ
Mode (MRS bit A12 set to “1”), where the on-die DLL is disabled in this mode of operation.
T
0
"low"
ODT Timing for Precharge Power-Down and Active Power-Down Mode
t
ANPD
t
IS
T
1
and
tAONPD,min
tAONPD,max
t
AXPD
T
2
) define if synchronous or asynchronous ODT timings have to be applied.
t
ANPD.MIN
t
IS
T
3
is satisfied
tAOFPDmax
tAOFPDmin
T
4
42
Rtt
can
asynchronous timing parameters apply.
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
be
T
5
applied.
T
6
If
512-Mbit DDR2 SDRAM
t
ANPD.MIN
T
7
Functional Description
09112003-SDM9-IQ3P
is
Rev. 1.6, 2005-08
T
8
not
ODT02
satisfied,

Related parts for hyb18t512160afl-3.7