hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 55

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

3.20
One write data mask input (DM) for ×4 and ×8
components and two write data mask inputs (LDM,
UDM) for ×16 components are supported on DDR2
SDRAM’s, consistent with the implementation on DDR
SDRAM’s. It has identical timings on write operations
as the data bits, and though used in a uni-directional
manner, is internally loaded identically to data bits to
Figure 36
Figure 37
RL = 3 (AL = 0, CL = 3), WL = 2,
Data Sheet
Write Data Mask
Write Data Mask Timing
Write Operation with Data Mask Example
t
WR
= 3, BL = 4
56
insure matched system timing. Data mask is not used
during read cycles. If DM is HIGH during a write burst
coincident with the write data, the write data bit is not
written to the memory. For ×8 components the DM
function is disabled, when RDQS / RDQS are enabled
by EMRS(1).
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
09112003-SDM9-IQ3P
Rev. 1.6, 2005-08