z86131 ZiLOG Semiconductor, z86131 Datasheet - Page 8

• Manufacturer Part Number: z86131
• Description: Ntsc Line 21 Decoder
• Manufacturer: ZiLOG Semiconductor

Z86129/130/131
NTSC Line 21 Decoder
PIN DESCRIPTIONS (Z86129 ONLY)
Inputs
VIDEO (Pin 7).
(nom), band limited to 600 kHz. The circuit operates with
signal variation between 0.7–1.4V p-p. The polarity is sync
tips negative. This signal pin should be AC coupled through
a 0.1 µF capacitor and driven by a source impedance of 470
ohms or less.
HIN (Pin 5).
must be supplied. When the device is used in VIDEO LOCK
mode, this signal pulls the on-chip VCO within the proper
range. The circuit uses the frequency of this signal which
must be within +3% F
used in the H LOCK mode, the VCO phase locks to the ris-
ing edge of this signal. The HPOL bit of the H Position reg-
ister can be set to operate with either polarity of input signal
(usually the H Flyback signal). The timing difference be-
tween HIN rising edge and the leading edge of composite
sync (of VIDEO input) is one of the factors which affects
the horizontal position of the display. Any shift resulting
from the timing of this signal can be compensated for with
the horizontal timing value in H Position Register. H LOCK
is intended for use when the part is generating an OSD dis-
play when no video signal is present.
SMS (Pin 6).
When this input is at a CMOS High state (1) the Serial Con-
trol Port operates in the SPI mode. When the input is Low
(0), the Serial Control Port operates in the I
In SPI mode, the SEN pin must be tied High. (See Reset
Operation section, below.)
SEN (Pin 4).
the Serial Control Port. When this pin is Low (0), the SPI
port is disabled and the SDO pin is in the high-impedance
state. Transitions on the SCK and SDA pins are ignored.
SPI mode operation is enabled when SMS is High (1).
SCK (Pin 15).
master control device. In I
is expected to be within I
imum clock frequency is 10 MHz.
Reset Operation.
in the Low (0) state, the part is in the Reset state. Therefore,
in the I
When SPI mode is used, if three wire operation is desired,
both SMS and SEN can be tied together and used as the
NReset input. In either mode, NReset must be held Low (0)
for at least 100 ns.
8
2
C mode the SEN pin can be used as an NReset input.
Horizontal Sync input signal at CMOS level
Enable signal for the SPI mode operation of
Mode select pin for the Serial Control Port.
Input pin for serial clock signal from the
Composite NTSC video input, 1.0V p-p
When the SMS and SEN pins are both
h
but can be of either polarity. When
2
2
C limits. In SPI mode, the max-
C mode operation the clock rate
2
C slave mode.
P R E L I M I N A R Y
Input/Output
V
of operation, the internal vertical sync circuits lock to the
V
rising or falling edge of the signal in accordance with the
setting of the V Polarity command. The default is rising
edge. The V
In INTRO Mode, when configured for internal vertical syn-
chronization, this pin is an output pin providing an interrupt
signal to the master control device in accordance with the
settings in the Interrupt Mask Register.
SDA (Pin 14).
I
line for sending and receiving serial data. In SPI mode op-
eration it operates as serial data input. SPI mode output data
is available on the SDO pin.
Outputs
SDO (Pin 16).
mode communications have been selected. This pin is not
used in I
Box (Pin 17).
CMOS level signal used to key in the black box in the cap-
tions/text displays. This output is in the high-impedance
state when the background attribute is set to semi-transpar-
ent.
RED, GREEN, BLUE (Pins 2, 3, 18).
CMOS levels signals.
Color Mode: Red, Green and Blue character video outputs
for use in a color receiver.
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Note: The selection of Color/Mono Mode is user controlled in
CSync (Pin 8).
be tied between this pin and analog ground V
capacitor stores the sync slice level voltage.
LPF (Pin 9).
be tied between this pin and analog ground V
must also be second capacitor from the pin to V
2
IN
IN
C mode operation, this pin serves as the bidirectional data
/INTRO (Pin 13).
Mono Mode: All three outputs carry the character lumi-
nance information
input signal applied at this pin. The part locks to the
bit D
(See Internal Registers section, page 33).
2
C mode operation.
1
IN
Loop Filter. A series RC low-pass filter must
of the Configuration Register (Address=00h).
Black box keying output is an active High,
When the Serial Control Port has been set to
pulse must be at least 2 lines wide.
Provides the serial data output when SPI
Sync slice level. A 0.1-µF capacitor must
In external (EXT) vertical lock mode
DS007200-TVX0199
P o s i t i v e a c t i n g
SS
SS
(A). There
SS
(A). This
(A).
ZiLOG