z86131 ZiLOG Semiconductor, z86131 Datasheet - Page 12

• Manufacturer Part Number: z86131
• Description: Ntsc Line 21 Decoder
• Manufacturer: ZiLOG Semiconductor

Z86129/130/131
NTSC Line 21 Decoder
Z86129/130/131 BLOCK DIAGRAM DESCRIPTION (Continued)
Timing and Counting Circuits
The Dot Clk is first divided down to produce the character
timing clock CHAR CLK. This signal is then further divid-
ed to generate the horizontal timing signals, H, 2H and
HSQR. These timing signals are used in the data output (dis-
play) circuits.
The H signal is further divided in the LINE and FLD CNTR
to produce the various decodes used to establish vertical
lock and to time the display and control functions required
for proper operation. The H signal is also used to generate
the Smooth Scroll timing signal for display.
The V Lock circuits produce a noise free vertical pulse de-
rived from the horizontal timing signal. When the user se-
lects Video as the vertical lock source, the internal synchro-
nizing signals are phased up with the incoming video by
comparing the internally generated vertical pulse to an input
vertical pulse derived from the Comp Sync signal provided
by the Sync Slicer. In the vertical lock set to V
V
Sync. In either case, when proper phasing has been estab-
lished, this circuit outputs the LOCK signal which is used
to provide additional noise immunity to the slicing circuits.
The LOCKed state is established only after several succes-
sive fields have occurred in which these two vertical pulses
remain in sync. When LOCKed, the internal timing fly-
wheels until such time as the two vertical pulses lose coin-
cidence for a number of consecutive fields. Until LOCK is
established, the decoder operates on a pulse for pulse basis.
Command Processor
The Command Processor circuit controls the manipulation
of the data for storage and display. It processes the Control
Port input commands to determine the display status desired
and the data channel selected. During the display time (lines
43–237), this information is used to control the loading, ad-
dressing and clearing of the Display RAM and the opera-
tions of the Character ROM and Output Logic circuits.
During data recovery time (TV lines 21–42), the Command
Processor, in conjunction with the data recovery circuits,
recovers the XDS data and the data for the selected data
channel. Data is sent to the RAM for storage and display
and/or to the serial port, as appropriate. Where necessary,
the Command Processor converts the input data to the ap-
propriate form.
12
IN
signal is used in place of the signal derived from Comp
IN
mode the
P R E L I M I N A R Y
Output Logic (Z86129 only)
The output logic circuits operate together to generate the
output color signals RED, GREEN and BLUE and the Box
signal. When MONOchrome mode is selected all three col-
or outputs carry the Luminance information. These outputs
are positive output logic signals.
The character ROM contains the dot pattern for all the char-
acters. The output logic provides the hardware underline,
graphics characters and the Italics slant generator circuits.
The smooth scroll display is achieved by the smooth scroll
counter logic controlling the addressing of the Character
ROM.
Decoder Control Circuit
The Decoder Control circuit block is the users communi-
cations port. It converts the information provided to the con-
trol port into the internal control signals required to estab-
lish the operating mode of the decoder. This port can be
operated in one of two serial modes. The SMS pin is used
to establish the serial control mode to be used.
In the two-wire (I
spond to its slave address for both the read and write con-
ditions. If the read bit is Low (indicating a WRITE se-
quence) then the Z86129/130/131 responds with an
acknowledge. The master should then send an address byte
followed by a data byte. If the read bit is High (indicating
a READ sequence) then the Z86129/130/131 responds with
an acknowledge followed by a status byte then a data byte.
Read data is only available through indirect addressing.
Write addressing exhibits both indirect and direct modes.
The busy bit in the status byte indicates if the write operation
has been completed or if read data is available.
The SPI mode is a three wire bus with the Z86129/130/131
performing as the slave device. Communication is synchro-
nized by the SCK signal generated by the master. Typically,
the serial data output is transmitted on the falling edge of
SCK and the received data is captured on the rising edge
of SCK. All data is exchanged as 8-bit bytes.
Voltage/Current Reference
The Voltage/Current reference circuit uses an externally
connected resistor to establish the reference levels that are
used throughout the Z86129/130/131. The use of an exter-
nal resistor provides improved internal precision at minimal
additional cost.
2
C) control mode, the Z86129/130/131 re-
DS007200-TVX0199
ZiLOG