z86131 ZiLOG Semiconductor, z86131 Datasheet - Page 25

• Manufacturer Part Number: z86131
• Description: Ntsc Line 21 Decoder
• Manufacturer: ZiLOG Semiconductor

ZiLOG
Writing to the I
All write commands are either one or two byte commands.
The Z86129/130/131 is enabled when a Start condition fol-
lowed by its Slave Address Write byte is received. It is dis-
abled when it deems the command to have been completed
or by a Stop condition. A new Start condition without a Stop
condition begins a new sequence. Therefore, successive
commands may be executed by successive strings of
“Start—Slave Address—Command” sequences without
any intervening Stop condition being sent.
Note: The number of data bytes to be received by the
A write to the Z86129/130/131 should always be preceded
b y e x e c u t i n g a S t a t u s r e a d t o v e r i f y t h a t t h e
Z86129/130/131 is not busy. The Status register data is out-
put immediately following the reception of the Slave Ad-
dress Read. If the RDY bit is set, the master device can ini-
tiate its write sequence, always beginning with the Start
condition. The first byte of a two byte command is always
written first.
An example of the master’s sequence for writing a two-byte
command (after RDY had been checked) would be:
DS007200-TVX0199
I 2 C One-Byte Write (Command)
Note:
or to the STRT condition of either WRITE sequence. See One
Byte Read (Status Only) in Figure 13 for more information on
reading the Status Register.
I 2 C Two-Byte Write (Command & Data)
Start
Slave Address
Write/Slave ACK COMMAND (master)/Slave ACK
DATA (master)/Slave ACK
Stop
Z86129/130/131 is inherent in the command and the
Z86129/130/131 responds with the acknowledge signal
only for the number of bytes expected. If the master
writes more bytes than expected, there is no acknowl-
edge for the extra bytes.
Status Register RDY bit must be read and checked pri-
Figure 12. I
STRT
STRT
(WRITE=28h)
(WRITE=28h)
SLAVE
ADDR
SLAVE
ADDR
2
C Bus
2
C Bus WRITE (Command)
COMMAND
COMMAND
WRITE
WRITE
STOP
WRITE
DATA
P R E L I M I N A R Y
STOP
Reading Data Using the I
With the exception of the Serial Status (SS) register, which
may be read at any time, each read operation must be set
up before the data can be read from the serial output registers
of the Z86129/130/131. Data is set up for a read operation
either automatically or manually. XDS data reads are set up
automatically upon recovery by setting a valid XDS FIL-
TER register selection. All other data read operations must
be set up manually using the READ SELECT commands
RDS1 and RDS2. These commands load the selected data
byte or pair of bytes into the serial output register(s), set the
SS register RD2 bit according to the number of data bytes
requested and set the SS register DAV bit to indicate avail-
ability of data.
The Z86129/130/131 I
byte read sequences. All read sequences output the SS reg-
ister as the first output byte. If the serial status DAV bit is
set, a two or three byte read sequence can then be initiated,
beginning with a new STRT condition. If the DAV bit is
not set, the I
data bytes or the desired data can be lost from the
Z86129/130/131output registers.
The number of data bytes available is indicated by the state
of the RD2 bit of the serial status. In a typical read operation
the status byte is read and the DAV and RD2 bits are ex-
amined. If one or two data bytes are available they are read
in sequence separated by acknowledges.
Note: In all I
The master’s sequence for reading two
three bytes including SSB) from the Z86129/130/131 is as:
Start
Slave Address Read/Slave ACK
SS Byte/Master ACK
Byte (slave)/Master ACK
Byte (slave)/Master NACK
Stop
defined in Figure 13) the most recent byte read from the
Z86129/130/131 should be acknowledged by the master
with a NACK (Not ACKnowledge). It is also necessary
to read all available data in a read operation to clear the
DAV bit and permit subsequent reads. DAV is cleared by
the master clocking out the eighth bit of the most recent
data-byte read. DAV is never cleared by just reading the
SSB (one-byte read) alone. All data is output MSB first.
2
C master device should not attempt to read any
2
C Read operations (one, two, and three byte as
2
C Bus supports one, two and three
2
C Bus
NTSC Line 21 Decoder
data bytes
Z86129/130/131
(total of
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