z86131 ZiLOG Semiconductor, z86131 Datasheet - Page 30

• Manufacturer Part Number: z86131
• Description: Ntsc Line 21 Decoder
• Manufacturer: ZiLOG Semiconductor

Z86129/130/131
NTSC Line 21 Decoder
COMMANDS (Continued)
Note:
er has no affect on the current display mode in operation.
Read And Write Commands
Read Selects.
(RDS1 and RDS2) in the Z86129/130/131. Each command
is one byte in size and indicates that a read should take place.
RDS1 specifies that one byte are read from the
Z86129/130/131. Likewise, RDS2 indicates that two bytes
are read.
RDS1 = 40hÐ47h.
initiate a one-byte read sequence by moving the contents
of the register identified by the address field (AD00:02) of
the command to the output register. Addresses 0h–7h are
valid in the RDS1 command field AD00:02.
RDS2 = 60hÐ66h.
used to initiate a two byte read sequence by moving the con-
tents of the two consecutive registers, starting with the one
identified by the address portion of the command
(AD00:AD02), to the output registers and setting the RD2
bit in the SS register. Only Addresses 0h–6h are valid in the
RDS2 command field AD00:02.
30
Figure 17. RSD2ÐRead Two Bytes (RDS2 = 60hÐ66h)
Bit
16 Second Erase
Bit
Figure 16. RDS1ÐRead One Byte (RDS1 = 40hÐ47h)
XDS Display
Command
CM7
W
W
XDSG
7
0
XDSF
0
Timer
Changing the ON/OFF state of the 16 Second Erase Tim-
Table 19. XDS Display Commands
CM6
W
1
W
1
6
There are two Read Select commands
CM5
RDS1 is a one-byte command used to
RDS2 is a one byte command which is
W
5
1
0
W
16 Sec Tmr ON
XDS Display Command Code
AD04
AD04
CM4
4
W
W
23h
21h
20h
AD03
AD03
CM3 CM2 CM1
3
W
W
AD02 AD01 AD00
AD02 AD01 AD00
W
2
16 Sec Tmr OFF
W
1
W
27h
25h
24h
W
P R E L I M I N A R Y
CM0
0
W
W
Note: For XDS data recovery, when the XDS Filter Register
Reading Data From The Z86129/130/131
READ1 = F8h.
READ2 = F9h.
mode.
The READx commands do not affect the status of the RDY
bit in the Serial Status (SS) register and can be executed in-
dependent of the RDY status.
In both serial communications modes, the DAV bit in the
SS register indicates when data is available. When the RD2
bit is Low, DAV is cleared on the rising edge of SCK at the
LSB of the first data byte. When the RD2 bit is High, DAV
is cleared on the rising edge of SCK at the LSB of the second
data byte. The RD2 bit is only valid if DAV is High.
Reading in the I
Slave Address byte. The first byte after the Slave Address
byte is SS followed by the data in output buffers A and B
in that order. If the instruction being executed is a one- byte
read, then buffer A contains the read data and buffer B con-
tains all ones.
Writing to the Z86129/130/131
WRxx = C0hÐDFh
Bit
Bit
W
7
1
W
1
(see Internal Registers section, page 33) is enabled for
the desired packets, the Z86129/130/131 automatically
establishes the two-byte recovery mode and move the re-
covered data bytes to the output register.
7
Figure 19. WRxxÐWrite Register xx
Figure 18. READxÐRead x Bytes
W
1
W
6
1
6
Command to read one byte in the SPI mode.
Command to read two bytes in the SPI
2
C mode is selected by the R/NW bit in the
(READ1/2 = F8h/F9h)
(WRx = C0hÐDFh)
W
5
1
5
W
0
AD04
4
1
W
4
W
AD03
W
1
W
3
3
DS007200-TVX0199
AD02 AD01 AD00
0
2
W
2
W
1
0
W
1
W
ZiLOG
RD2
W
W
0
0