z86131 ZiLOG Semiconductor, z86131 Datasheet - Page 11

• Manufacturer Part Number: z86131
• Description: Ntsc Line 21 Decoder
• Manufacturer: ZiLOG Semiconductor

ZiLOG
Z86129/130/131 BLOCK DIAGRAM DESCRIPTION
As discussed, the Z86129/130/131 are defined differently
for the requirements of Line 21 Data applications. However
the part number, Z86129, is used to describe the functions
of the block diagram. In this description, there are some de-
scriptions that are not applicable to the Z86130/131 for the
feature differences listed on page 1.
The Z86129 is designed to process both fields of Line 21
of the television VBI and provide the functional perfor-
mance of a Line 21 Closed-Caption decoder and Extended
Data Service decoder. It requires two input signals, Com-
posite Video and a horizontal timing signal (HIN), and sev-
eral passive components for proper operation. A vertical in-
put signal is also required if OSD display mode is desired
when no video signal is present. The Decoder performs sev-
eral functions, namely extraction of the data from Line 21,
separation of the normal Line 21 data from the XDS data,
on-screen display (Z86129 only) of the selected data chan-
nel and outputting of the XDS data through the serial com-
munications channel.
Input Signals
The Composite Video input should be a signal which is
nominally 1.0 Volt p-p with sync tips negative and band
limited to 600 kHz. The Z86129 operates with an input level
variation of ±3 dB.
The HIN input signal is required to bring the VCO close to
the desired operating frequency. It must be a CMOS level
signal. The HIN signal can have positive or negative polar-
ity and is only required to be within 3% of the standard H
frequency. When configured for EXT HLK operation, this
signal should correspond to the H Flyback signal.
The timing difference between HIN rising edge and the
leading edge of composite sync (of VIDEO input) is one
of the factors that affects the horizontal position of the dis-
play. Any shift resulting from the timing of this signal can
be compensated for with the horizontal timing value in the
H Position register.
Video Input Signal Processing
The Comp Video input is AC coupled to the device where
the sync tip is internally clamped to a fixed reference volt-
age by means of a dual clamp. Initially, the unlocked signal
is clamped using a simple clamp. Improved impulse noise
performance is then achieved after the internal sync circuits
lock to the incoming signal. Noise rejection is obtained by
making the clamp operative only during the sync tip. The
clamped composite video signal is fed to both the Data Slic-
er and Sync Slicer blocks.
DS007200-TVX0199
P R E L I M I N A R Y
The Data Slicer generates a clean CMOS level data signal
by slicing the signal at its midpoint. The slice level is es-
tablished on an adaptive basis during Line 21. The resultant
value is stored until the next occurrence of that Line 21. A
high level of noise immunity is achieved by using this pro-
cess.
The Sync Slicer processes the clamped Comp Video signal
to extract Comp Sync. This signal is used to lock the inter-
nally generated sync to the incoming video when the video
lock mode of operation has been enabled. Sync slicing is
performed in two steps. In the non-locked mode, the sync
is sliced at a fixed offset level from the sync tip. When prop-
er lock operation has been achieved, the slice level voltage
switches from a fixed reference level to an adaptive level.
The slice level is stored on the sync slice capacitor, CSYNC.
The Data Clock Recovery circuit operates in conjunction
with the Digital H Lock circuit. They produce a 32H clock
signal (DCLK) that is locked in phase to the clock run-in
burst portion of the sliced data obtained from the Data Slic-
er. When Line 21 code appears, DCLK phase lock is
achieved during the clock run-in burst and used to reclock
the sliced data. After phase lock is established it is main-
tained until a change in video signal occurs.
The Digital H Lock circuit produces the video timing gates,
PG, STG, and so on, which are locked in phase with
HSYNC, the video timing signal, no matter which H lock
mode is used in the display generation circuits. This inde-
pendent phase lock loop is able to respond quickly to chang-
es in video timing, without concern for display stability re-
quirements.
VCO and One Shot
All internal timing and synchronizing signals are derived
from the on-board 12-MHz VCO. Its output is the Dot Clk
signal used to drive the Horizontal and Vertical counter
chains and for display timing. The One Shot circuit pro-
duces a horizontal timing signal derived from the incoming
video and qualified by the Copy Guard logic circuits.
The VCO can be locked in phase to two different sources.
For television operation, where a good horizontal display
timing signal is available, the VCO is locked to the HIN in-
put through the action of the Phase Detector (PH2). When
a proper HIN signal is not available, such as in a VCR, the
VCO can be locked to the incoming video through the Phase
Detector (PH1). In this case, the frequency detector (FR)
circuit is activated as required to bring the VCO within the
pull-in range of PH1.
NTSC Line 21 Decoder
Z86129/130/131
11