z86131 ZiLOG Semiconductor, z86131 Datasheet - Page 26

• Manufacturer Part Number: z86131
• Description: Ntsc Line 21 Decoder
• Manufacturer: ZiLOG Semiconductor

Z86129/130/131
NTSC Line 21 Decoder
SERIAL COMMUNICATIONS INTERFACE (Continued)
Clock and Data Transitions.
are normally pulled High with a resistor. Data on the SDA
bus may only change during SCK Low time periods. Data
changes during SCK High periods indicate a start or stop
condition as defined in Table 16.
Start Condition.
SCK High is a start condition which must precede any other
command.
26
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
SCK
Low
High
R
F
AA
BUF
HD.STA
SU.STA
HD.DAT
SU.DAT
SU.STO
DH
I
I 2 C-One Byte Read (Status Only)
Note:
recent byte read from the Z86129/130/131 must be ac-
knowledged by the master with a NACK (Not ACKnowl-
edge).
I 2 C-Two Byte Read (Status & Data1)
I 2 C-Three Byte Read (Status, Data1, & Data2)
STRT
In all I
Figure 13. I
STRT
STRT
(READ=29h)
2
C Read operations defined herein, the most
SLAVE
ADDR
(READ=29h)
(READ=29h)
A High-to-Low transition of SDA with
SLAVE
SLAVE
ADDR
ADDR
Parameter
Clock Frequency
Clock Pulse Width Low
Clock Pulse Width High
SDA and SCL Rise Time
SDA and SCL Fall Time
Clock Low to Data Out Valid
Bus Free Time
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Stop Set-up Time
Data Out Hold Time
Input Filter Time Constant
2
C Bus READ (Command)
STATUS
SERIAL
(SSB)
STATUS
STATUS
SERIAL
SERIAL
(SSB)
(SSB)
The SCK and SDA bus lines
READ
DATA1
STOP
NACK
NACK
READ
DATA1
READ
DATA2
Table 16. I
STOP
NACK
P R E L I M I N A R Y
STOP
2
C Serial Timing
Stop Condition.
SCK High is a stop condition which terminates all commu-
nications.
Acknowledge.
transmitted to and from the Z86129/130/131 in eight-bit
words. A ninth-bit time is used for the acknowledge. The
device acknowledges by pulling the SDA bus Low during
the ninth bit. A Not Acknowledge (NACK) is provided by
SDA=High during the ninth clock time.
SDA (IN)
SDA (OUT)
SCK
Min
250
100
4.7
4.0
0.1
4.7
4.0
4.7
4.7
t
Ð
Ð
0
SU.STA
t
HD.STA
t
AA
t
Figure 14. I
F
All address and data words are serially
A Low-to-High transition of SDA with
t
HD.DAT
Max
t
100
300
100
1.0
3.5
High
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
2
C Serial Timing
t
Low
t
t
SU.DAT
DH
DS007200-TVX0199
Units
kHz
ns
ns
ns
ns
t
R
s
s
s
s
s
s
s
s
s
t
BUF
t
ZiLOG
SU.STO