psb21391 Infineon Technologies Corporation, psb21391 Datasheet - Page 75

• Manufacturer Part Number: psb21391
• Description: Siemens Codec With Upn Transceiver
• Manufacturer: Infineon Technologies Corporation

2.3.3
The receive PLL uses the 15.36-MHz clock to generate an internal 384-kHz signal which
is used to synchronize the PLL to the received U
signal as well as the 1.536-MHz double bit clock signal and the 768-kHz bit clock.
The length of the FSC signal pulse is reduced to one DCL period (“Short FSC”) at the
beginning of the second IOM frame after the received code violation in the M-bit. The
reduced length of the FSC-signal provides synchronization between the TE- and the TR-
transceiver to gain the shortest delays on the U
2.3.4
Figure 39
Data Delay between U
2.3.4.1
The lOM-interface B-channels are used to convey the two 64-kbit/s user channels in both
directions. However, the SCOUT-P(X) only transfers the data transparently in the
activated state (inc. analog loop activated) while the data are set to ‘1’ in any non
activated state.
2.3.4.2
The Stop/Go (S/G) bit can be controlled by the received U
state of the line card arbiter to the HDLC-controller of the terminal. If selected by the
DIM2-0 bits (’0x1’) in the MODEH register, the HDLC-transmitter evaluates the state of
the S/G-bit before and during transmission of an HDLC-frame.
Data Sheet
U
FSC
DU
DD
PN
B1
B1
U
Data Transfer and Delay between IOM and U
B1-, B2- and D-Channels
Stop/Go Bit
B1
B2 D
B2 D
PN
B2
Transceiver Timing
D B1
B2
BAC
CV
PN
B1
B1
and IOM
B1
B2 D
B2 D
B2
D B1
B2
CV
B1
B1
65
B1
B2 D
B2 D
B2
PN
D B1
PN
T-channel data forwarding.
frame. The PLL outputs the FSC-
B2
BAC
S/G
T
B1
B1
PN
PN
B1
B2 D
B2 D
T-channel to transmit the
B2
D B1
B2
T
line_iom_smartLink.vsd
PSB 21391
PSB 21393
Interfaces
2001-03-07