psb21391 Infineon Technologies Corporation, psb21391 Datasheet - Page 186

• Manufacturer Part Number: psb21391
• Description: Siemens Codec With Upn Transceiver
• Manufacturer: Infineon Technologies Corporation

Data Sheet
RFBS
Bit6
1
1
Note: A change of RFBS will take effect after a receiver command (CMDR.RMC,
SRA
0: Receive Address is not stored in the RFIFO
1: Receive Address is stored in the RFIFO
XCRC
0: CRC is transmitted
1: CRC is not transmitted
RCRC
0: CRC is not stored in the RFIFO
1: CRC is stored in the RFIFO
ITF
Selects the inter-frame time fill signal which is transmitted between HDLC-frames.
0: Idle (continuous ’1’)
1: Flags (sequence of patterns: ‘0111 1110’)
Note: ITF must be set to ’0’ for power down mode.
7.0.8
Value after reset: 00
TIMR
CMDR.RRES,) has been written
In applications with D-channel access handling (collision resolution), the only
possible inter-frame time fill is idle (continuous ’1’). Otherwise the D-channel on
the line interface can not be accessed
RFBS
Bit5
0
1
TIMR - Timer Register
7
… Store Receive Address
… Transmit CRC
… Receive CRC
… Interframe Time Fill
Block Size
Receive FIFO
8 byte
4 byte
CNT
H
5
4
176
VALUE
Detalled Register Description
0
RD/WR (24
PSB 21391
PSB 21393
2001-03-07
H
)