psb21391 Infineon Technologies Corporation, psb21391 Datasheet - Page 173

• Manufacturer Part Number: psb21391
• Description: Siemens Codec With Upn Transceiver
• Manufacturer: Infineon Technologies Corporation

6.5
During each reset the reference voltage (V
clocks (DCL) keep running.
During a reset caused by the undervoltage detection the microcontroller clock
(pin MCLK) is stopped. In all other cases the microcontroller clock is running.
During any reset that has an influence on the IOM handler (see figure 80) the pin FSC
is set to ’1’, the pin SDS1 is set to ’0’ and pin BCL, DD and DU are in the high-impedance
state.
During any reset that has an influence on the codec (see figure 80) the pins LSP, LSN,
HOP and HON are in the high-impedance state.
During any reset that has an influence on the transceiver (see figure 80) the pins LIa
and LIb are in the high-impedance state.
During hardware reset or a reset caused by the undervoltage detection the pins SDX and
INT are in the high-impedance state.
A hardware reset and a reset caused by the undervoltage detection is always output at
pin RSTO/SDS2. This reset will be released by the falling edge of BCL following the
release of the pin RST (if the undervoltage detection is disabled) or after 64 ms (if the
undervoltage detection is enabled).
Data Sheet
Pin Behavior during Reset
163
REF
) stays applied, the oscillator and data
PSB 21391
PSB 21393
2001-03-07
Reset