m66291 Renesas Electronics Corporation., m66291 Datasheet - Page 63

• Manufacturer Part Number: m66291
• Description: Assp Usb2.0 Device Controller
• Manufacturer: Renesas Electronics Corporation.

M 6 6 2 9 1 G P / H P
2.31 Dn_FIFO Select Registers (n=0~1)
R e v 1 . 0 1
BUST
13~14
b15
D0_FIFO Select Register (D0_FIFO_SELECT)
D1_FIFO Select Register (D1_FIFO_SELECT)
5~4
3~0
15
12
11
10
0
-
-
b
9
8
7
6
2 0 0 4 . 1 1 . 0 1
BUST
Burst Mode
DFORM
Transfer Method
RWND
Buffer Rewind
ACKA
DACK Polarity
REQA
DREQ Polarity
INTM
DMA Interrupt Mode
DMAEN
DMA Enable
BSWP
Byte Swap Mode
Octl
Register 8-Bit Mode
Reserved. Set it to “0”.
DMA_EP
DMA Transfer Endpoint Designate
14
0
-
-
DFORM
13
0
-
-
p a g e 6 3 o f 1 2 2
RWND ACKA
12
0
-
-
Bit name
11
0
-
-
REQA
10
0
-
-
INTM DMAEN BSWP
9
0
-
-
0 :
1 :
00 : Controls by DACK signal and read/write signal
01 : Controls by DACK signal only
10 : Controls by chip select/address signal and read/write signal
11 : Reserved
<When set to OUT buffer>
0 :
1 :
<When set to IN buffer>
0 :
1 :
0 :
1 :
0 :
1 :
0 :
1 :
0 :
1 :
0 :
1 :
0 :
1 :
0001 :EP1 (Endpoint 1)
0010 :EP2 (Endpoint 2)
0011 :EP3 (Endpoint 3)
0100 :EP4 (Endpoint 4)
0101 :EP5 (Endpoint 5)
0110 :EP6 (Endpoint 6)
Other than those above : Invalid
Write
Write
8
0
-
-
Cycle Steal Transfer
Burst Transfer
Invalid (Ignored when written)
Clears the buffer reading pointer
Invalid (Ignored when written)
Clears the buffer writing pointer
"L" active
"H" active
"L" active
"H" active
Sets “1” to EPB_RDY bit by completion of DMA transfer
Sets “1” to EPB_RDY bit by completion of receiving
Disable DMA transfer
Enable DMA transfer (assertion of DREQ signal)
Byte is treated as little ENDIAN
Byte is treated as big ENDIAN
Dn_FIFO Data Register is 16-bit mode
Dn_FIFO Data Register is 8-bit mode
7
0
-
-
Octl
6
0
-
-
Function
5
0
-
-
4
0
-
-
3
0
-
-
2
0
-
-
DMA_EP
<H/W reset : H'0000>
<Address : H’48>
<Address : H’50>
<USB bus reset : ->
<S/W reset : ->
1
0
-
-
R
0
0
b0
0
-
-
W
0