m66291 Renesas Electronics Corporation., m66291 Datasheet - Page 46

• Manufacturer Part Number: m66291
• Description: Assp Usb2.0 Device Controller
• Manufacturer: Renesas Electronics Corporation.

M 6 6 2 9 1 G P / H P
2.23 EP0_FIFO Select Register
R e v 1 . 0 1
(1) RCNT (Read Count Mode) Bit (b15)
(2) Octl (Register 8-Bit Mode) Bit (b10)
RCNT
14~11
b15
EP0_FIFO Select Register (EP0_FIFO_SELECT)
9~8
6~1
15
10
0
-
-
b
7
0
This bit sets the countdown methods of the ODLN bits at the time of reading the EP0_FIFO Data Register.
When this bit is set to “0”, the ODLN bit value does not change in spite of reading the data from the EP0_FIFO
Data Register, and is cleared to H’0 when all data is read out.
When this bit is set to “1”, the ODLN bit values are counted down every time the data is read from the
EP0_FIFO Data Register. Here, the down-count value differs as shown below depending on whether the
EP0_FIFO Data Register is set to 8-bit mode or 16-bit mode:
This bit sets the access mode of the EP0_FIFO Data Register.
When this bit is set to “0”, the EP0_FIFO Data Register is set to 16-bit mode, and all bits of the EP0_FIFO
Data Register are valid.
When this bit is set to “1”, the EP0_FIFO Data Register is set to 8-bit mode, and the upper-order 8 bits of the
EP0_FIFO Data Register (b15 to b8) are invalid.
Set this bit before receiving the data.
When set to control write transfer (ISEL bit = “0”), change this bit before receiving the data. When set to
control read transfer (ISEL bit = “1”), if the E0req bit indicates “1”, do not change this bit.
This bit becomes invalid (fixed to 8-bit mode) when the mode is set to 8-bit by *HWR/*BYTE pin.
In such case, this bit is read “0”.
2 0 0 4 . 1 1 . 0 1
Note
RCNT
Read Count Mode
Reserved. Set it to “0”.
Octl
Register 8-Bit Mode
Reserved. Set it to “0”.
BSWP
Byte Swap Mode
Reserved. Set it to “0”.
ISEL
Buffer Select
14
0
-
-
•
•
: Use the *HWR/*BYTE pin or the Octl bit of this register for setting the 8-bit/16-bit mode.
8-bit mode
16-bit mode
13
0
-
-
p a g e 4 6 o f 1 2 2
12
0
-
-
Bit name
11
0
-
-
: Down-count per “-1”
: Down-count per “-2”
Octl
10
0
-
-
9
0
-
-
0:
1:
0 :
1 :
0 :
1 :
0 :
1 :
8
0
-
-
The ODLN bits are cleared by reading all receive data
The ODLN bits are counted down by reading receive data
EP0_FIFO Data Register is 16-bit mode
EP0_FIFO Data Register is 8-bit mode
Byte is treated as little ENDIAN
Byte is treated as big ENDIAN
Control write transfer
Control read transfer
BSWP
7
0
-
-
6
0
-
-
Function
5
0
-
-
4
0
-
-
3
0
-
-
2
0
-
-
<H/W reset : H'0000>
<Address : H’30>
<USB bus reset : ->
<S/W reset : ->
1
0
-
-
R
0
0
0
ISEL
b0
0
-
-
W
0
0
0