m66291 Renesas Electronics Corporation., m66291 Datasheet - Page 54

• Manufacturer Part Number: m66291
• Description: Assp Usb2.0 Device Controller
• Manufacturer: Renesas Electronics Corporation.

M 6 6 2 9 1 G P / H P
2.27 CPU_FIFO Select Register
R e v 1 . 0 1
(1) RCNT (Read Count Mode) Bit (b15)
RCNT
14~13
b15
11~8
CPU_FIFO Select Register (CPU_FIFO_SELECT)
5~4
3~0
15
12
0
-
-
b
7
6
This bit sets the countdown methods of the CPU_DTLN bits at the time of reading the CPU_FIFO Data
Register.
When this bit is set to “0”, the CPU_DTLN bit value does not change in spite of reading the data from the
CPU_FIFO Data Register, and is cleared to H’0 when all data is read out.
When this bit is set to “1”, the CPU_DTLN bit values are counted down every time the data is read from the
CPU_FIFO Data Register. Here, the down-count value differs as shown below depending on whether the
CPU_FIFO Data Register is set to 8-bit mode or 16-bit mode:
2 0 0 4 . 1 1 . 0 1
Note
RCNT
Read Count Mode
Reserved. Set it to “0”.
RWND
Buffer Rewind
Reserved. Set it to “0”.
BSWP
Byte Swap Mode
Octl
Register 8-Bit Mode
Reserved. Set it to “0”.
CPU_EP
CPU Access Endpoint Designate
14
0
-
-
•
•
: Use the *HWR/*BYTE pin or the Octl bit of this register for setting the 8-bit/16-bit mode.
8-bit mode
16-bit mode
13
0
-
-
p a g e 5 4 o f 1 2 2
RWND
12
0
-
-
Bit name
11
0
-
-
: Down-count per “-1”
: Down-count per “-2”
10
0
-
-
9
0
-
-
0:
1:
<When set to OUT buffer>
0 :
1 :
<When set to IN buffer>
0 :
1 :
0 :
1 :
0 :
1 :
0001 :EP1 (Endpoint 1)
0010 :EP2 (Endpoint 2)
0011 :EP3 (Endpoint 3)
0100 :EP4 (Endpoint 4)
0101 :EP5 (Endpoint 5)
0110 :EP6 (Endpoint 6)
Other than those above : Invalid
Write
Write
8
0
-
-
The CPU_DTLN bits are cleared by reading all receive
data
The CPU_DTLN bits are counted down by reading receive
data
Invalid (Ignored when written)
Clears the buffer reading pointer
Invalid (Ignored when written)
Clears the buffer writing pointer
Byte is treated as little ENDIAN
Byte is treated as big ENDIAN
CPU_FIFO Data Register is 16-bit mode
CPU_FIFO Data Register is 8-bit mode
BSWP
7
0
-
-
Octl
6
0
-
-
Function
5
0
-
-
4
0
-
-
3
0
-
-
2
0
-
-
CPU_EP
<H/W reset : H'0000>
<Address : H’40>
<USB bus reset : ->
<S/W reset : ->
1
0
-
-
R
0
0
0
0
b0
0
-
-
W
0
0
0