m66291 Renesas Electronics Corporation., m66291 Datasheet - Page 31

• Manufacturer Part Number: m66291
• Description: Assp Usb2.0 Device Controller
• Manufacturer: Renesas Electronics Corporation.

M 6 6 2 9 1 G P / H P
R e v 1 . 0 1
(5) CTRT (Control Transfer Stage Transition Interrupt) Bit (b11)
(6) BEMP (Buffer Empty/Size Over Error Interrupt) Bit (b10)
(7) INTN (Buffer Not Ready Interrupt) Bit (b9)
(8) INTR (Buffer Ready Interrupt) Bit (b8)
(9) Vbus (Vbus Level) Bit (b7)
(10) DVSQ (Device State) Bits (b6~b4)
Note : SCKE bit = “0” when XCKE bit = “1 ”, or XCKE bit = “0”.
This bit indicates the transition of stage in control transfers.
This bit is set to “1” when the stage transition of control transfer takes place as follows (control transfer stage
transition interrupt occurs):
Refer to Figure 2.7.
The Conditions that this bit indicates "1" depend on the WDST, RDST, CMPL or SERR bits.
This bit is cleared to “0” by writing “0” (interrupt is cleared).
The present stage can be confirmed by the CTSQ bits.
This bit indicates the occurrence of “buffer empty” or “buffer size over error”.
This bit is set to “1” when the EPB_EMP_OVR bit is set to “1” (buffer empty/buffer size over error interrupt
occurs).
This bit is cleared by setting all the bits of Interrupt Status Register 3 to “0”.
For details, refer to “Interrupt Status Register 3”.
This bit indicates the NAK has been sent to the host because of the “buffer not ready” state.
This bit is set to “1” when the EPB_NRDY bit is set to “1” (buffer not ready interrupt occurs).
This bit is cleared by setting all the bits of Interrupt Status Register 2 to “0”.
For details, refer to “Interrupt Status Register 2”.
This bit indicates the “buffer ready” state (that can be read/written).
This bit is set to “1” when the EPB_RDY bit is set to “1” (buffer ready interrupt occurs).
This bit is cleared by setting all the bits of Interrupt Status Register 1 to “0”.
For details, refer to “Interrupt Status Register 1”.
This bit indicates the state of Vbus pin.
When this bit changes, the VBUS bit is set to “1”.
This bit is capable of reading the correct value even if the clock is not supplied (Note).
These bits indicate the present device states as follows:
Depending on the changes of these device states, the DVST bit and the RESM bit are set to “1” (set
enable/disable by the URST, SADR, SCFG or SUSP bits). For details, refer to “DVST bit” and Figure 2.6.
2 0 0 4 . 1 1 . 0 1
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000 : Powered State
001 : Default State
010 : Address State
011 : Configured State
1xx : Suspended State
Setup Stage Complete (When transmitting ACK)
Control Write Transfer Status Stage Transition (When receiving IN token)
Control Read Transfer Status Stage Transition (When receiving OUT token)
Control Transfer Complete (When transmitting or receiving ACK)
Control Transfer Sequence Error (When error occurs)
p a g e 3 1 o f 1 2 2
Power ON state
USB bus reset detected state
SET_ADDRESS request executed state
SET_CONFIGURATION request executed state
“suspended” detected state