m66291 Renesas Electronics Corporation., m66291 Datasheet - Page 23

• Manufacturer Part Number: m66291
• Description: Assp Usb2.0 Device Controller
• Manufacturer: Renesas Electronics Corporation.

M 6 6 2 9 1 G P / H P
R e v 1 . 0 1
(1) VBSE (Vbus Interrupt Enable) Bit (b15)
(2) RSME (Resume Interrupt Enable) Bit (b14)
(3) SOFE (SOF Detect Interrupt Enable) Bit (b13)
(4) DVSE (Device State Transition Interrupt Enable) Bit (b12)
(5) CTRE (Control Transfer Transition Interrupt Enable) Bit (b11)
(6) BEMPE (Buffer Empty/Size Over Error Interrupt Enable) Bit (b10)
(7) INTNE (Buffer Not Ready Interrupt Enable) Bit (b9)
(8) INTRE (Buffer Ready Interrupt Enable) Bit (b8)
(9) URST (USB Reset Detect) Bit (b7)
(10) SADR (SET_ADDRESS Execute) Bit (b6)
This bit sets enable/disable of Vbus interrupt.
When this bit is set to “1”, the interrupt occurs if VBUS bit is set to “1”.
This bit is capable of writing/reading even if the clock is not supplied (Note).
This bit sets enable/disable of resume interrupt.
When this bit is set to “1”, the interrupt occurs if RESM bit is set to “1”.
This bit is capable of writing/reading even if the clock is not supplied (Note).
This bit sets enable/disable of SOF detect interrupt.
When this bit is set to “1”, the interrupt occurs if SOFR bit is set to “1”.
This bit sets enable/disable of device state transition interrupt.
When this bit is set to “1”, the interrupt occurs if DVST bit is set to “1”.
The Conditions the DVST bit set are depend on the URST, SADR, SCFG or SUSP.
This bit sets enable/disable of control transfer transition interrupt.
When this bit is set to “1”, the interrupt occurs if CTRT bit is set to “1”.
The Conditions the DVST bit set are depend on the WDST, RDST, CMPL or SERR.
The complete of setup stage can not set enable/disable to set CTRT bit to “1”.
This bit sets enable/disable of buffer empty/size over error interrupt.
When this bit is set to “1”, the interrupt occurs if BEMP bit is set to “1”.
This bit sets enable/disable of buffer not ready interrupt.
When this bit is set to “1”, the interrupt occurs if INTN bit is set to “1”.
This bit sets enable/disable of buffer ready interrupt.
When this bit is set to “1”, the interrupt occurs if INTR bit is set to “1”.
This bit selects whether to set the DVST bit to “1” or not at the USB bus reset detection.
The register is initialized by the USB reset detection, irrespective of the value of this bit.
This bit selects whether to set the DVST bit to “1” or not at the SET_ADDRESS execution.
For details, refer to “DVST bit”.
2 0 0 4 . 1 1 . 0 1
Note :
Note :
At SCKE bit = “0” when XCKE bit = “1 ” or XCKE bit = “0”.
At SCKE bit = “0” when XCKE bit = “1 ” or XCKE bit = “0”.
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