m66291 Renesas Electronics Corporation., m66291 Datasheet - Page 29

• Manufacturer Part Number: m66291
• Description: Assp Usb2.0 Device Controller
• Manufacturer: Renesas Electronics Corporation.

M 6 6 2 9 1 G P / H P
R e v 1 . 0 1
(1) VBUS (Vbus Interrupt) Bit (b15)
Note : x is a optional value.
6~4
2~0
b
7
3
Note : SCKE bit = “0” when XCKE bit = “1 ”, or XCKE bit = “0”.
The b15 to b8 of this register are interrupt status bits. When the bit of the Interrupt Enable Register
corresponding to these bits are set to “1” (interrupt enable), the interrupt occurs by setting these bits to “1”.
This bit indicates the change of Vbus input.
This bit is set to “1” (Vbus interrupt occurs) when the Vbus input changes (“L”->“H” or “H”->“L”).
This bit is cleared to “0” by writing “0” (interrupt is cleared).
This bit is set to “1” and can be read out even if the clock is not supplied (Note). This bit can also be cleared by
writing “0”. In case the clock is not supplied, make sure to write “1” after writing “0” (no further interrupt will
be accepted).
2 0 0 4 . 1 1 . 0 1
Vbus
Vbus Level
DVSQ
Device State
VALID
Setup Packet Detect
CTSQ
Control Transfer Stage
p a g e 2 9 o f 1 2 2
Bit name
0 :
1 :
Invalid (Ignored when written)
000 : Powered state
001 : Default state
010 : Address state
011 : Configured state
1xx : Suspended state (Note)
Invalid (Ignored when written)
0 :
1 :
0 :
1 :
000 : Idle or setup stage
001 : Control read transfer data stage
010 : Control read transfer status stage
011 : Control write transfer data stage
100 : Control write transfer status stage
101 : Control write no data transfer status stage
110 : Control transfer sequence error
111 : Reserved
Invalid (Ignored when written)
Read
Write
Read
Write
Read
Write
Read
Write
"L"
"H"
No detection
Receiving the setup packet
This VALID bit clear
Invalid (Ignored when written)
Function
R
W
×
×
×