m66291 Renesas Electronics Corporation., m66291 Datasheet

m66291

Manufacturer Part Number

m66291

Description

Assp Usb2.0 Device Controller

Manufacturer

Renesas Electronics Corporation.

Datasheet

1.M66291.pdf (126 pages)

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Download datasheet (897Kb)

M66291GP/HP

ASSP (USB2.0 Device Controller)

1.1 Features

R e v 1 . 0 1

Overview

Specification Revision 2.0 and supports full speed transfer. The USB transceiver circuit is included, and the M66291

meets all transfer types which are defined in the USB specification. The M66291 has FIFO of 3 Kbytes for data

transfer and can set 7 endpoints (maximum). Each endpoint can be set programmable of its transfer condition, so can

correspond to each device class transfer system of USB.

The M66291 is a general purpose USB (Universal Serial Bus) device controller compliant with the USB

Applications

Support all PC peripheral built-in USB

USB Specification Revision 2.0 compliant

Supports Full Speed (12 Mbps) transfer

Built-in USB transceiver circuit

Built-in oscillation buffer (Supports 6M/12M/24 MHz of oscillator) and PLL at 48 MHz

Supports Vbus direct connection (5 V withstand voltage input), D+ pin pullup output

Supports all transfer type which is defined in the USB specification.(Control transfer / Bulk transfer / Interrupt

Low power consumption operation (Average 15 mA at operation)

Robust against signal distortion on USB transfer line due to SIE/DPLL(Digital Phase Lock Loop) of the original

Easy making enumeration program and timing design because hardware manages the device state / control

Reduction of CPU load due to continuous transmit/receive mode (the mode for buffering several transaction data

Up to 7 endpoints (EP0 to EP6) selectable

Data transfer condition selectable for each endpoint (EP1 to EP6)

Built-in FIFO buffer (3 Kbytes) for endpoints

Buffering conditions of FIFO memory settable per endpoint (EP1 to EP6)

Four pieces of configurable FIFO ports

”Interrupt queuing function” that eliminates the need of complicated factor analysis

Connectable to various CPU/DMAC

FIFO access cycle of maximum 24 Mbytes/sec

2 0 0 4 . 1 1 . 0 1

transfer / Isochronous transfer)

design

transfer state (transition timing)

into FIFO) This enables high performance and throughput improvement.

Compatible to various applications (device class)

• Data transfer type

• Transfer direction

• Packet size

• FIFO buffer size (up to 1Kbyte)

• Presence/Absence of double buffer configuration (setting of buffer size x 2)

• Endpoint number allocation

• Access method switching (CPU, DMAC)

• Bit width (8-bit / 16-bit)

• Endian switching

• Bus width(8-bit / 16-bit)

• Interface voltage(2.7V to 5.5V)

• Interrupt signal and DMA control signal polarities settable

• Supports multi-word DMA (burst)

p a g e 1 o f 1 2 2

(Bulk transfer / Isochronous transfer / Interrupt transfer)

(IN, OUT)

REJ03F0125-0101Z

2004.11.01

Rev1.01

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