com20020-5 Standard Microsystems Corp., com20020-5 Datasheet - Page 51
![no-image](/images/no-image-200.jpg)
com20020-5
Manufacturer Part Number
com20020-5
Description
Com20020-5 Ulanc Universal Local Area Network Controller With 2k X 8 On-board Ram
Manufacturer
Standard Microsystems Corp.
Datasheet
1.COM20020-5.pdf
(58 pages)
- Current page: 51 of 58
- Download datasheet (253Kb)
A0-A2
nCS
DIR
nDS
D0-D7
FIGURE 13A - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE
**nCS may become active after control becomes active, but the data setup time will
*
Note 1:
Note 2: Any cycle occurring after a write to the Address Pointer Low Register
now be 30 nS measured from the later of nCS falling or Valid Data available.
T is the Arbitration Clock Period.
T is identical to XTAL1 if SLOW ARB = 0,
T is twice XTAL1 period if SLOW ARB = 1
t1
t2
t3
t4
t5
t6
t7
t8
t9
Address Setup to nDS Active
Address Hold from nDS Inactive
nCS Setup to nDS Active
nCS Hold from nDS Inactive
DIR Setup to nDS Active
Cycle Time (nDS Low to Next Time Low)**
DIR Hold from nDS Inactive
Valid Data Setup to nDS High
Data Hold from nDS High
requires a minimum of 4T from the trailing edge of nDS to the leading
edge of the next nDS.
The Microcontroller typically accesses the COM20020-5 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020-5 cycles.
Parameter
t1
t5
t3
CYCLE
51
VALID
t6
VALID DATA
t8
30**
min
4T*
15
10
10
10
10
5
0
max
t9
t2
t7
Note 2
t4
t6**
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
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