com20020-5 Standard Microsystems Corp., com20020-5 Datasheet
com20020-5
Related parts for com20020-5
com20020-5 Summary of contents
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... Command Chaining for Top Performance Reduced Reconfiguration Times Sequential Access to Internal RAM Software Programmable Node ID Duplicate Node ID Detection Powerful Diagnostics SMSC's COM20020 member of the family of Industrial Network Controllers from Standard Microsystems Corporation. The device is a special purpose communications controller for networking ...
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... Corporation. For more detailed information on cabling options including RS485, transformer-coupled RS- 485 and Fiber Optic interfaces, please refer to the following technical note which is available from Standard Microsystems Corporation: Technical Note 7-5 - Cabling Guidelines for the COM20020 ULANC. 80 Arkay Drive Hauppauge, NY 11788 (516) 435-6000 ...
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... DEVICE TYPE: 20020-5 = Universal Local Area Network Controller The integration of the 2Kx8 RAM buffer on-chip, the Command Chaining feature, the 5 Mbps maximum data rate, and the internal diagnostics make the COM20020-5 the highest performance industrial communications device available. With only one microcontroller, a complete communications node may be implemented ...
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... On an 80XX-like bus, this active low signal is issued by the microcontroller to indicate a write operation. In this case, a logic "0" on this pin, when the COM20020-5 is accessed, enables data from the data bus to be written to the device. 4 ...
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... It is used to activate the internal reset circuitry within the COM20020-5. nINTR Output. This active low signal is generated by the COM20020-5 when an enabled interrupt condition occurs. nINTR returns to its inactive state when the interrupt status condition or the corresponding interrupt mask bit is reset. ...
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Crystal Oscillator 24 15,28 Power Supply 12 7,14,22 Ground MISCELLANEOUS XTAL1, An external crystal should be connected to XTAL2 these pins external TTL clock is used instead, it must be connected to XTAL1 with a 390 ...
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... NID refers to the next identification number that receives the token after - after this ID passes it. SID refers to the source identification DID refers to the destination identification. SOH refers to the start of header character; preceeds all data packets. - FIGURE 1 - COM20020-5 OPERATION Free Buffer Enquiry to this ID ...
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... COM20020-5 connected MHz crystal oscillator. PROTOCOL DESCRIPTION DATA RATES The COM20020-5 is capable of supporting data rates from 312.5 Kbps following protocol description assumes a 5 Mbps data rate. internal clock divider scales down the clock frequency. Thus all timeout values are scaled ...
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... When any COM20020-5 senses an idle line for greater than 41 S, which occurs only when the token is lost, each COM20020-5 starts an internal timeout equal times the quantity 255 minus its own ID. The COM20020- 5 starts network reconfiguration by sending an invitation to transmit first to itself and then to all other nodes by decrementing the destination Node ID ...
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... NETWORK RECONFIGURATION, activity will appear on the line every 41 S. This equal to the Response Time of 37.35 S plus the time it takes the COM20020-5 to start retransmitting another message (usually another INVITATION TO TRANSMIT). Reconfiguration Time (ET1, ET2) If any node does not receive the token within the Reconfiguration Time, the node will initiate a NETWORK RECONFIGURATION ...
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Data Packets A Data Packet consists of the actual data being sent to another node sent by the following sequence: An ALERT BURST An SOH (Start Of Header--ASCII code 01H) An SID (Source ID) character Two (repeated) DID ...
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... Since microcontrollers do not typically have peripherals cannot extend cycles to extend the access time. COM20020-5, on the other hand fast that it does not need to limit the speed of the microcontroller. The COM20020-5 is designed to be flexible so that it is independent of the microcontroller speed. The COM20020-5 provides for no wait state ...
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... GND nINTR Differential Driver Configuration AO/nMUX * Media Interface may be replaced with Figure MHz +5V +5V RXIN 100 Ohm nPULSE1 +5V NOTE: COM20020-5 must be in Backplane Mode FIGURE B 13 75ALS176B or Equiv. 2 Receiver 6 HFD3212-002 7 Transmitter HFE4211-014 Fiber Interface (ST Connectors) ...
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... XTAL1 XTAL2 D0- nRES nIOS R/nW nIRQ1 6801 47 pF FIGURE 3 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 COM20020-5 D0-D7 A0/nMUX RXIN A1 A2/BALE nCS TXEN nPULSE1 nRESET IN nPULSE2 GND nRD/nDS nWR/DIR Differential Driver nINTR Configuration 40 MHz INTERFACE 14 75ALS176B or Equiv. * Media Interface may be replaced ...
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... Note that when used in the open-drain mode, the COM20020-5 does not have a fail/safe input on the RXIN pin. The nPULSE1 signal actually contains a weak pull-up resistor. This pull-up should not take the place of the resistor required on the media for open drain mode ...
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... The transmitter portion RT 75ALS176B or Equiv. COM20020-5 FIGURE 4 – COM20020-5 NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS COM20020-5 is disabled during reset and the cost-sensitive nPULSE1, nPULSE2 and nTXEN pins are direct inactive. Programmable TXEN Polarity To accommodate transceivers with active high ...
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ADDRESS DECODING CIRCUITRY AD0-AD2, D3-D7 STATUS/ nINTR COMMAND REGISTER RESET nRESET IN LOGIC nRD/nDS nWR/DIR BUS ARBITRATION nCS CIRCUITRY RECONFIGURATION FIGURE 5 - INTERNAL BLOCK DIAGRAM RAM ADDITIONAL REGISTERS MICRO- TX/RX SEQUENCER LOGIC AND WORKING REGISTERS OSCILLATOR ...
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... The COM20020-5 derives a 10MHz and a 5MHz clock from the external crystal. These clocks provide the rate at which the instructions are executed within the COM20020-5. The 10MHz clock is the rate at which the program counter operates, while the 5MHz clock is the rate at which the instructions are executed ...
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... The Duplicate ID bit of the Diagnostic Status Register helps the user find a unique Node ID. Refer to the Initialization Sequence section for further detail on the use of the DUPID bit. The core of the COM20020-5 does not wake up until a Node ID other than zero is written into the Node ID Register. During this time, no ...
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TABLE 1 - READ REGISTER SUMMARY REGISTER MSB STATUS RI X MY- DIAG. DUPID RCVACT RECON STATUS AUTO- ADDRESS RDDATA PTR INC HIGH ADDRESS PTR LOW DATA RESERVED X X CONFIG- CCHEN TXEN RESET ...
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TABLE 2 – WRITE REGISTER SUMMARY ADDRESS MSB AUTO- 02 RDDATA 0 INC RESET CCHEN TXEN TID7 TID6 TID5 ...
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... High Register and then to Low Register. Configuration Register The Configuration Register is a read/write register which is used to configure the different modes of the COM20020-5. The Configuration Register defaults to the value 0001 1000 upon hardware reset only. Setup Register The Setup Register is a read/write 8-bit register ...
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... NAK. These bits are undefined. This bit, if high, indicates that the COM20020-5 has been reset by either a software reset, a hardware reset, or writing 00H to the Node ID Register. The POR bit is cleared by the "Clear Flags" command. ...
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TABLE 4 - DIAGNOSTIC STATUS REGISTER BIT BIT NAME SYMBOL 7 My Reconfiguration MY- RECON 6 Duplicate ID DUPID 5 Receive RCVACT Activity 4 Token Seen TOKEN 3 Excessive NAK EXCNAK 2 Tentative ID TENTID 1 New Next ID NEW ...
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... Disable This command will cancel any pending receive command. Receiver COM20020-5 is not yet receiving a packet, the RI (Receiver Inhibited) bit will be set to logic "1" the next time the token is received. reception is already underway, reception will run to its normal conclusion. b0fn n100 ...
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... Address 7-0 A7-A0 DESCRIPTION This bit tells the COM20020-5 whether the following access will be a read or write. A logic "1" prepares the device for a read, a logic "0" prepares it for a write. This bit controls whether the address pointer will increment automatically. A logic "1" on this bit allows automatic increment of the pointer after each access, while a logic " ...
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... Sub Address 1,0 SUBAD 1,0 DESCRIPTION A software reset of the COM20020-5 is executed by writing a logic "1" to this bit. A software reset does not reset the microcontroller interface mode, nor does it affect the Configuration Register. The only registers that the software reset affect are the Status Register, the Interrupt Mask Register, and the Diagnostic Status Register. This bit must be brought back to logic " ...
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... ID. This feature can be used to put the COM20020 'listen-only' mode, where the transmitter is disabled and the COM20020-5 is not passing tokens. Defaults low. These bits are used to determine the data rate of the COM20020-5. The following table is for a 40MHz crystal: CKP3 CKP2 ...
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Data Register I/O Address 04H D0-D7 Address Pointer Register I/O Address 02H High 11-Bit Counter FIGURE 6 - SEQUENTIAL ACCESS OPERATION Memory Data Bus 8 I/O Address 03H Low Memory Address Bus INTERNAL RAM ...
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... Access Speed The COM20020-5 is able to accommodate very fast access cycles to its registers and buffers. Arbitration to the buffer does not slow down the cycle because the pointer based access method allows data to be prefetched from memory and ...
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... During a transmit sequence, the microcontroller selects a 256 or 512 byte segment of the RAM buffer and writes into it. The appropriate buffer size is specified in the "Define Configuration" command. When long packets are enabled, the COM20020-5 interprets the packet as either a long or short packet, depending on whether the 31 The ...
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SHORT PACKET FORMAT ADDRESS SID 0 1 DID COUNT = 256-N 2 NOT USED COUNT DATA BYTE 1 DATA BYTE 2 DATA BYTE N-1 255 DATA BYTE N NOT USED 511 N = DATA PACKET LENGTH SID = SOURCE ID ...
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... The first possibility free buffer is available at the destination node, in which case it responds with an ACKnowledgement. At this point, the COM20020-5 fetches the data from the Transmit Buffer and performs the transmit sequence successful transmit sequence is completed, the TMA bit and the TA bit are set to logic " ...
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... RAM buffer other than the SID and DID. The Once the packet is received and stored correctly if the in the selected buffer and the checksum matches the packet, the COM20020-5 sets the the RI bit to logic "1" to signal the microcontroller that the reception is complete. 34 There is no way of ...
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... Through the use of a dual two-level FIFO, commands to be transmitted and received, as well as the status bits, are pipelined. In order for the COM20020 compatible with previous SMSC ARCNET device drivers, the device defaults to the non-chaining mode. In order to take advantage of the Command Chaining operation, the Command Chaining Mode must be enabled via a logic " ...
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... Interrupt" command is issued. Note that the interrupt will remain active until the command is issued, and the second interrupt will not occur until the first interrupt is acknowledged. COM20020-5 guarantees a minimum of 100nS interrupt inactive time interval interrupts. The TMA bit is also double buffered to reflect whether the appropriate transmission was a success ...
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... In the COM20020-5, the Receive Inhibit (RI) bit of the Interrupt Mask Register now masks only the TRI bit of the Status Register, not the RI bit as in the non-chaining mode. Since the TRI bit ...
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... ET1 and ET2 bits are other than 1,1). To determine if another node on the network already has this ID, the COM20020-5 compares the value in the Node ID Register with the DID's of the token, and determines whether there is a response to it. Once the Diagnostic Status Register is read, the DUPID bit is cleared ...
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MYRECON bit of the Diagnostic Register. Reading the Diagnostic Status Register resets the MYRECON bit. Successive occurrences of a logic "1" on the MYRECON bit indicates that a problem exists with this node. At that point, the transmitter should be ...
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... EC400-40.0000 40 MHz 47pF FIGURE 9 – OSCILLATOR CIRCUIT OSCILLATOR The COM20020-5 contains circuitry which, in conjunction with an external parallel resonant crystal or TTL clock, forms an oscillator external crystal is used, two capacitors and one resistor are needed (one from each leg of the crystal to ground). ...
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... Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists it is suggested that a clamp circuit be used. DC ELECTRICAL CHARACTERISTICS COM20020-5I PARAMETER SYMBOL ...
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PARAMETER SYMBOL Low Output Voltage 1 V OL1 (nPULSE in Normal Mode, nPULSE2, nTXEN) High Output Voltage 1 V OH1 (nPULSE1 in Normal Mode, nPULSE2, nTXEN) Low Output Voltage 2 V OL2 (D0-D7) High Output Voltage 2 V OH2 (D0-D7) ...
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CAPACITANCE ( 1MHz Output and I/O pins capacitive load specified as follows: PARAMETER SYMBOL Input Capacitance C IN Output Capacitance 1 C OUT1 (All outputs except nPULSE1 in BackPlane Mode) Output Capacitance ...
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... T is identical to XTAL1 if SLOW ARB = twice XTAL1 period if SLOW ARB = 1 Note 1: The Microcontroller typically accesses the COM20020-5 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20020-5 cycles. FIGURE 10 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE ...
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... T is identical to XTAL1 if SLOW ARB = twice XTAL1 period if SLOW ARB = 1 Note 1: The Microcontroller typically accesses the COM20020-5 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20020-5 cycles. FIGURE 10A - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE ...
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... T is the Arbitration Clock Period identical to XTAL1 if SLOW ARB = twice XTAL1 period if SLOW ARB = 1 The Microcontroller typically accesses the COM20020-5 on every other cycle. Note 1: Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20020-5 cycles. ...
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... T is the Arbitration Clock Period identical to XTAL1 if SLOW ARB = twice XTAL1 period if SLOW ARB = 1 Note 1: The Microcontroller typically accesses the COM20020-5 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20020-5 cycles. ** ...
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... Note 1: The Microcontroller typically accesses the COM20020-5 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20020-5 cycles. FIGURE 12 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE ...
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... The Microcontroller typically accesses the COM20020-5 on every other cycle. Note 1: Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20020-5 cycles. ...
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... Valid Data available. The Microcontroller typically accesses the COM20020-5 on every other cycle. Note 1: Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20020-5 cycles ...
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... Valid Data available. Note 1: The Microcontroller typically accesses the COM20020-5 on every other cycle. Therefore, the cycle time specified in the microcontroller's datasheet should be doubled when considering back-to-back COM20020-5 cycles. ...
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RXIN Parameter t1 nPULSE1, nPULSE2 Pulse Width t2 nPULSE1, nPULSE2 Period t3 nPULSE1, nPULSE2 Overlap t4 nTXEN Low to nPULSE1 Low** t5 Beginning of Last Bit Time to nTXEN High** t6 RXIN Pulse ...
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Clk) t10 RXIN t11 Parameter t1 nPULSE2 High to nTXEN Low t2 nPULSE1 Pulse Width t3 nPULSE1 Period t4 nPULSE2 Low to nPULSE1 Low t5 nPULSE2 High Time t6 nPULSE2 Low Time t7 ...
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XTAL1 Parameter t1 Input Clock High Time t2 Input Clock Low Time t3 Input Clock Period t4 Input Clock Frequency FIGURE 16 – TTL INPUT TIMING ON XTAL1 PIN t1 nRESET IN nINTR Parameter t1 nRESET IN Pulse Width ...
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G PIN NO DIM NOTES: 1. All dimensions are in inches. 2. Circle indicating pin 1 can appear on a top surface as shown on the drawing or right above beveled edge. ...
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D Base Plane Seating Plane Note: All dimensions are in inches. FIGURE 18A - 24-PIN DIP PACKAGE DIMENSIONS DIM 24L A .090-.200 A1 .020-.065 A2 .145-.155 B .016-.021 B1 .060-.070 ...
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... COM20020-5 ERRATA SHEET PAGE SECTION/FIGURE/ENTRY 8 Network Protocol 9 Network Reconfiguration 9 Extended Timeout Function 9 Response Time 10 Idle Time 10 Reconfiguration Time 10 Line Protocol 10 Invitations to Transmit 10 Free Buffer Enquiries 11 Acknowledgements 11 Negative Acknowledgements 12 Microcontroller Interface 15 Backplane Configuration 16 Programmable TXEN Polarity 19 Data Register 19 Status Register 22 Address Pointer Registers ...
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... Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. COM20020-5 Rev. 4/14/95 ...