com20020-5 Standard Microsystems Corp., com20020-5 Datasheet - Page 18

• Manufacturer Part Number: com20020-5
• Description: Com20020-5 Ulanc Universal Local Area Network Controller With 2k X 8 On-board Ram
• Manufacturer: Standard Microsystems Corp.

MICROSEQUENCER
The
microsequencer which performs all of the
control operations necessary to carry out the
ARCNET protocol.
generator, a 544 x 8 ROM, a program counter,
two instruction registers, an instruction decoder,
a
reconfiguration logic.
The COM20020-5 derives a 10MHz and a 5MHz
clock from the external crystal. These clocks
provide the rate at which the instructions are
executed within the COM20020-5. The 10MHz
clock is the rate at which the program counter
operates, while the 5MHz clock is the rate at
which the instructions are executed. The
microprogram is stored in the ROM and the
instructions are fetched and then placed into the
instruction registers.
opcode, while the other holds the immediate
data.
decoded by the internal instruction decoder, at
which point the COM20020-5 proceeds to
execute the instruction.
instruction is encountered, the microsequencer
enters a timed loop and the program counter is
temporarily stopped until the loop is complete.
When a jump instruction is encountered, the
program counter is loaded with the jump
address from the ROM.
contains an internal reconfiguration timer which
interrupts the microsequencer if it has timed out.
the MYRECON bit of the Diagnostic Status
Register is set.
INTERNAL REGISTERS
The
registers.
COM20020-5 register map. Reserved locations
should not be accessed.
are read as undefined and must be written as
logic "0".
At this point the program counter is cleared and
no-op
COM20020-5
COM20020-5
Once the instruction is fetched, it is
Tables 1 and 2 illustrate the
generator,
contains
It consists of a clock
contains
One register holds the
jump
The COM20020-5
All undefined bits
When a no-op
eight
FUNCTIONAL DESCRIPTION
an
logic,
internal
internal
and
18
Interrupt Mask Register (IMR)
The COM20020-5 is capable of generating an
interrupt signal when certain status bits become
true. A write to the IMR specifies which status
bits will be enabled to generate an interrupt. The
bit positions in the IMR are in the same position
as their corresponding status bits in the Status
Register and Diagnostic Status Register. A logic
"1"
corresponding interrupt.
capable of generating an interrupt include the
Receiver Inhibited bit, New Next ID bit,
Excessive NAK bit, Reconfiguration Timer bit,
and Transmitter Available bit. No other Status
or Diagnostic Status bits can generate an
interrupt.
The five maskable status bits are ANDed with
their respective mask bits, and the results are
ORed to produce the interrupt signal. An RI
or
corresponding mask bit is reset to logic "0", but
will reappear when the corresponding mask bit
is set to logic "1" again, unless the interrupt
status condition has been cleared by this time.
A RECON interrupt is cleared when the "Clear
Flags" command is issued.
interrupt is cleared when the "POR Clear Flags"
command is issued. A New Next ID interrupt is
cleared by reading the New Next ID Register.
The Interrupt Mask Register defaults to the
value 0000 0000 upon either hardware or
software reset.
Data Register
This read/write 8-bit register is used as the
channel through which the data to and from the
RAM passes. The data is placed in or retrieved
from the address location presently specified by
the address pointer. The contents of the Data
Register are undefined upon hardware reset. In
case of READ operation, the Data Register is
loaded with the contents of COM20020-5
TA
in
a
interrupt
particular
is
position
masked
The Status bits
An EXCNAK
enables
when
the
the