com20020-5 Standard Microsystems Corp., com20020-5 Datasheet - Page 35

• Manufacturer Part Number: com20020-5
• Description: Com20020-5 Ulanc Universal Local Area Network Controller With 2k X 8 On-board Ram
• Manufacturer: Standard Microsystems Corp.

COMMAND CHAINING
The
consecutive transmissions and receptions to
occur without host microcontroller intervention.
Through the use of a dual two-level FIFO,
commands to be transmitted and received, as
well as the status bits, are pipelined.
In order for the COM20020-5 to be compatible
with previous SMSC ARCNET device drivers,
the device defaults to the non-chaining mode. In
order to take advantage of the Command
Chaining operation, the Command Chaining
Mode must be enabled via a logic "1" on bit 6 of
the Configuration Register.
In Command Chaining, the Status Register
appears as in Figure 8.
The following is a list of Command Chaining
guidelines for the software programmer. Further
detail can be found in the Transmit Command
Chaining and Receive Command Chaining
sections.
The device is designed such that the interrupt
service routine latency does not affect
performance.
two outstanding receptions can be pending
at any given time. The commands may be
given in any order.
Up to two outstanding transmissions and
TRI
TRI
Command
MSB
FIGURE 8 – COMMAND CHAINING STATUS REGISTER QUEUE
RI
Chaining
operation
TA
POR
allows
35
TEST
Transmit Command Chaining
When the processor issues the first "Enable
Transmit
COM20020-5 responds in the usual manner by
resetting the TA and TMA bits to prepare for the
transmission from the specified page. The TA
bit can be used to see if there is currently a
transmission pending, but the TA bit is really
meant to be used in the non-chaining mode
only. The TTA bits provide the relevant
information for the device in the Command
and two outstanding receive interrupts are
stored by the device, along with their
respective status bits.
Transition on Transmitter Available) for
transmit
Transition of Receiver Inhibited) for receive
operations. TTA is set upon completion of
a packet transmission only. TRI is set upon
completion of a packet reception only.
Typically there is no need to mask the TTA
and TRI bits after clearing the interrupt.
available to reflect the present status of the
device.
Up to two outstanding transmit interrupts
The Interrupt Mask bits act on TTA (Rising
The traditional TA and RI bits are still
RECON
to
operations
Page
TMA
TMA
fnn"
and
command,
TRI
TTA
TTA
LSB
(Rising
the