com20020-5 Standard Microsystems Corp., com20020-5 Datasheet - Page 28

• Manufacturer Part Number: com20020-5
• Description: Com20020-5 Ulanc Universal Local Area Network Controller With 2k X 8 On-board Ram
• Manufacturer: Standard Microsystems Corp.

3,2,1
BIT
7
6
5
4
0
Pulse1 Mode
Four NACKS
ET3
Receive All
Clock Prescaler Bits
3,2,1
Slow Arbitration Select
BIT NAME
P1MODE
FOUR
NACKS
ET3
RCVALL
CKP3,2,1
SLW-ARB
SYMBOL
TABLE 9- SETUP REGISTER
This bit determines the type of PULSE1 output driver used in
Backplane Mode. When high, a push/pull output is used. When
low, an open drain output is used. The default is open drain.
This bit, when set, will cause the EXNACK bit in the Diagnostic
Status Register to set after four NACKs to Free Buffer Enquiry are
detected by the COM20020-5. This bit, when reset, will set the
EXNACK bit after 128 NACKs to Free Buffer Enquiry. The default
is 128.
This bit, when set, scales down protocol timeout values of
Response Time and Idle Time but NOT Reconfiguration Time to
optimize network performance in short topologies.
scaling factor of
ARCNET compliant.
This bit, when set, allows the COM20020-5 to receive all valid data
packets on the network, regardless of their destination ID. This
mode can be used to implement a network monitor with the
transmitter on- or off-line. Note that ACKs are only sent for packets
received with a destination ID equal to the COM20020-5's
programmed node ID.
COM20020-5 in a 'listen-only' mode, where the transmitter is
disabled and the COM20020-5 is not passing tokens. Defaults low.
These bits are used to determine the data rate of the COM20020-5.
NOTE: The lowest data rate achievable by the COM20020-5 is
312.5Kbs. A divide by 256 is provided for those systems that use
faster clock speeds. Defaults to 000 or 5Mbs.
This bit, when set, will divide the arbitration clock by 2. Memory
cycle times will increase when slow arbitration is selected. The
SLOWARB bit must be set for 5Mbs operation.
NOTE: For clock speeds greater than 20MHz, SLOWARB must be
set. Defaults to low.
The following table is for a 40MHz crystal:
CKP3
0
0
0
0
1
1
1
1
28
CKP2
0
0
1
1
0
0
1
1
CKP1
3. Defaults to a zero. Must be reset to be
0
1
0
1
0
1
0
1
DESCRIPTION
This feature can be used to put the
DIVISOR
128
256
16
32
64
8
312.5Kbs
Reserved
Reserved
Reserved
1.25Mbs
SPEED
625Kbs
2.5Mbs
5Mbs
Provides a