peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 339

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Data Sheet
SYNCH(7:0) Synchronization Character (high)
SYNCL(7:0) Synchronization Character (low)
This register is only valid in BISYNC protocol mode.
The synchronization (SYNC) character format depends on the setting of
bit ’BISNC’ and ’SLEN’ in register CCR1:
• MONOSYNC Mode (CCR1.BISNC = ’0’)
• BISYNC Mode (CCR1.BISNC = ’1’)
In transmit direction the SYNC character is sent continuously if no data
has to be transmitted and interframe timefill control is enabled by setting
bit ’ITF’ to ’1’ in register CCR2.
In receive direction the receiver monitors the data stream for occurence
of the specified SYNC pattern if operating in ’HUNT’ mode (bit ’HUNT’ in
register CMDR).
The SYNC character is defined by bit field ’SYNCL’:
a) SLEN = ’0’: the 6 bit SYNC character is specified by bits (5..0)
b) SLEN = ’1’: the 8 bit SYNC character is specified by bits (7..0).
The SYNC character is defined by bit fields ’SYNCL’ and ’SYNCH’:
a) SLEN = ’0’: the 12 bit SYNC character is specified by bits (5..0) of
each bit field, i.e. SYNC(11..0) = SYNCH(5..0), SYNCL(5..0)
b) SLEN = ’1’: the 16 bit SYNC character is specified by bits (7..0) of
each bit field, i.e. SYNC(15..0) = SYNCH(7..0), SYNCL(7..0).
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Detailed Register Description
(bisync mode)
(bisync mode)
PEB 20534
PEF 20534
2000-05-30