peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 303

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Data Sheet
SXIF
CRL
OIN
Selects Transmission of I-Frames
This bit is valid in HDLC-Automode only:
SXIF=’0’
SXIF=’1’
CRC Reset Value
This bit defines the initial value of the internal transmit/receive CRC
generators:
CRL=’0’
CRL=’1’
One Insertion
In HDLC mode a one-insertion mechanism similar to the zero-insertion
can be activated:
OIN=’0’
OIN=’1’
The SCC in Automode transmits transparent HDLC
frames (U-frames). No acknowledgement is awaited.
Causes the SCC in Automode to transmit a HDLC frame
as an I-frame. Additionally to the opening flag sequence,
the address and control field of the frame is automatically
added by the SCC. An all-sent (ALLS) interrupt is
generated after receiving the corresponding
acknowledgement
Initial value is 0xFFFF
(32 bit CRC).
Initial value is 0x0000
(32 bit CRC).
The ’1’ insertion mechanism is disabled.
In transmit direction a logical ’1’ is inserted to the serial
data stream after 7 consecutive zeros.
In receive direction a ’1’ is deleted from the receive data
stream after receiving 7 consecutive zeros.
This enables clock information to be recovered from the
receive data stream by means of a DPLL, even in the case
of NRZ data encoding, because a transition at bit cell
boundary occurs at least every 7 bits.
303
H
H
(16 bit CRC), 0x00000000
(16 bit CRC), 0xFFFFFFFF
Detailed Register Description
(bisync mode)
PEB 20534
PEF 20534
(hdlc mode)
(hdlc mode)
2000-05-30
H
H