peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 209

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

After start procedure the continuous operation of data transfer is essentially controlled
by the host and the DMAC sharing the data structures and interrupt queues located in
the memory.
Table 32
Step
1
2
3
4
5
Data Sheet
Action by Host
HOLD bit ctrld.
Add list elements to linked list, if
available.
Set HOLD=’1’ in
new last element
of linked list and
reset HOLD bit in
the previously last
descriptor.
Set
poll bit in GCMDR
register
GCMDR.TXPRi.
Serve interrupts appropriately.
Continuous Operation of Data Transfer
appropriate
Write
transmit/receive
descriptor
address in LTDA/
LRDA register.
LTDx/FTDx ctrld. HOLD bit ctrld.
new
209
last
Action by DSCC4 (DMAC)
The
transfers
between
memory and on
chip FIFOs.
It branches to the
next descriptor as
long as
HOLD = ’0’.
If HOLD=1 has
been
before, the DMAC
reads
descriptor
and
(HOLD=0) to next
descriptor.
Otherwise the poll
request is ignored.
Generally, host initiated interrupts
might be generated.
Reset and Initialization Procedure
branches
sensed
current
shared
DMAC
again
data
The
transfers
between
memory and on
chip FIFOs.
It branches to the
next descriptor as
long as FxDA is
not equal to LxDA.
If FTDA/FRDA =
LTDA/LRDA has
been
before, the DMAC
compares FTDA/
FRDA to updated
LTDA/LRDA and
branches to next
descriptor.
LTDx/FTDx ctrld.
PEB 20534
PEF 20534
2000-05-30
sensed
shared
DMAC
data