peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 207

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

9.3
After having performed the initialization, the host requests the activation of the DSCC4
by enabling the SCC(s) and setting the corresponding bits in the GCMDR.
A correct sequence is:
• activation of the SCC
• activation of the DMAC (receive and transmit)
• enabling the SCC receiver
Table 31
Step
1
2
3
4
5
6
7
8
Data Sheet
Action by Host
Set appropriate command bits for
interrupt queue initialization and
Action Request (AR) bit in GCMDR.
Serve interrupts.
Set the SCC to power-up mode via
CCR0.PU.
The SCC receiver should remain
disabled (CCR2.RAC=’0’).
Reset SCC transmitter.
Serve interrupts.
Start of Operation
Activation of DMAC and SCC
207
Action by DSCC4
The DMAC sets up the interrupt
queues. When the configuration was
successful,
GSTAR.ARACK=’1’.
If enabled, INT signal is activated and
the DMAC stores the corresponding
configuration interrupt vector in the
interrupt queue IQCFG located in the
shared memory.
The SCC requests for data from the
central TFIFO and, if data are
available, data transmission is started.
Receive/transmit interrupts caused by
the SCC are forwarded as interupt
vectors through the central interrupt
queue to the appropriate interrupt
buffers in shared memory.
Reset and Initialization Procedure
the
DMAC
PEB 20534
PEF 20534
2000-05-30
sets