isp1505a NXP Semiconductors, isp1505a Datasheet - Page 28

• Manufacturer Part Number: isp1505a
• Description: Isp1505a; Isp1505c Ulpi Hi-speed Universal Serial Bus Host And Peripheral Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1505A_ISP1505C_1
Product data sheet
9.6 Register read and write operations
RxActive:
RxActive event to the link. An RxActive event can be communicated using two methods.
The first method is for the ISP1505 to simultaneously assert DIR and NXT. The second
method is for the ISP1505 to send an RXCMD to the link with the RxActive field in
RxEvent bits set to logic 1. The link must be able to detect both methods. RxActive frames
the receive packet from the first byte to the last byte.
The link must assume that RxActive is set to logic 0 when indicated in an RXCMD or when
DIR is de-asserted, whichever occurs first.
The link uses RxActive to time high-speed packets and ensure that bus turnaround times
are met. For more information on the USB packet timing, see
RxError:
de-asserts NXT and sends an RXCMD with the RxError field set to logic 1. The received
packet is no longer valid and must be dropped by the link.
HostDisconnect:
HostDisconnect is valid only when the ISP1505 is configured as a host (both
DP_PULLDOWN and DM_PULLDOWN are set to logic 1), and indicates to the Host
Controller when a peripheral is connected or disconnected. The Host Controller must
enable HostDisconnect by setting the HOST_DISCON_R and HOST_DISCON_F bits in
the USB Interrupt Enable Rising Edge and USB Interrupt Enable Falling Edge registers,
respectively. Changes in HostDisconnect will cause the PHY to send an RXCMD to the
link with the updated value.
Figure 8
addressing and extended addressing register operations. Extended register addressing is
optional for links. Note that register operations will be aborted if the ISP1505 unexpectedly
asserts DIR during the operation. When a register operation is aborted, the link must retry
until successful. For more information on register operations, refer to UTMI+ Low Pin
Interface (ULPI) Specification Rev. 1.1 .
shows register read and write sequences. The ISP1505 supports immediate
When the ISP1505 has detected an error while receiving a USB packet, it
When the ISP1505 has detected a SYNC pattern on the USB bus, it signals an
HostDisconnect is encoded into the RxEvent field of the RXCMD.
Rev. 01 — 19 October 2006
ULPI HS USB host and peripheral transceiver
ISP1505A; ISP1505C
Section
9.8.1.
© NXP B.V. 2006. All rights reserved.
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