isp1505a NXP Semiconductors, isp1505a Datasheet - Page 21

• Manufacturer Part Number: isp1505a
• Description: Isp1505a; Isp1505c Ulpi Hi-speed Universal Serial Bus Host And Peripheral Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1505A_ISP1505C_1
Product data sheet
Fig 4. Power-up and reset sequence required before the ULPI bus is ready for use
DATA[7:0]
REG1V8
REG1V8
V
detector
internal
CLOCK
CLOCK
(output)
internal
(output)
CC(I/O)
XTAL1
(input)
XTAL1
(input)
POR
V
NXT
STP
DIR
CC
t1 = V
configured as an input, the V
delayed with respect to V
t2 = ULPI pads detect REG1V8 rising above the REG1V8 regulator threshold and are not in 3-state. These pads may drive
either LOW or HIGH. It is recommended that the link ignores the ULPI pins status during t
t3 = The POR threshold is reached and the POR pulse is generated. After the POR pulse, ULPI pins are driven to a defined
level. DIR is driven to HIGH and the other pins are driven to LOW.
t4 = The 19.2 MHz or 26 MHz input clock starts. This clock may be started any time.
t5 = The internal PLL is stabilized after t
will be stabilized after t
to LOW. The DIR pin will remain LOW before the link issues a RESET command to the ISP1505.
t6 = The power-up sequence is completed and the ULPI bus interface is ready for use.
CC
and V
CC(I/O)
t1
are applied to the ISP1505. The ISP1505 regulator starts to turn on. If the ISP1505 CLOCK pin is
t
PWRUP
startup(PLL)
CC
t2
, input clock mode stability cannot be guaranteed.
CC(I/O)
t3
from POR. The CLOCK pin starts to output 60 MHz. The DIR pin will transition from HIGH
power must be provided at the same time as the V
t4
startup(PLL)
Rev. 01 — 19 October 2006
t
startup(PLL)
. If the 19.2 MHz or 26 MHz clock is started before POR, the internal PLL
t5
internal clocks stable
RESET command
TXCMD
ULPI HS USB host and peripheral transceiver
D
ISP1505A; ISP1505C
CC
internal reset
power. If the V
PWRUP
.
CC(I/O)
© NXP B.V. 2006. All rights reserved.
power input is
RXCMD
update
004aaa885
bus idle
t6
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