isp1505a NXP Semiconductors, isp1505a Datasheet - Page 11

• Manufacturer Part Number: isp1505a
• Description: Isp1505a; Isp1505c Ulpi Hi-speed Universal Serial Bus Host And Peripheral Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1505A_ISP1505C_1
Product data sheet
7.10.9.1 RESET_N
7.10.9.2 PSW_N
7.10.7 REG3V3 and REG1V8
7.10.8 XTAL1 and XTAL2
7.10.9 RESET_N/PSW_N
Regulator output voltage. These supplies are used to power the ISP1505 internal digital
and analog circuits, and must not be used to power external circuits.
For correct operation of the regulator, it is recommended that you connect REG3V3 and
REG1V8 to decoupling capacitors. For an example, see
XTAL1 is the crystal input, and XTAL2 is the crystal output. The allowed frequency on the
XTAL1 pin depends on the ISP1505 product version.
If the link requires a 60 MHz clock from the ISP1505, then either a crystal must be
attached, or a clock of the same frequency must be driven into XTAL1, with XTAL2 left
floating. If the link drives a 60 MHz clock into the CLOCK pin, then XTAL1 must be
connected to REG1V8, and XTAL2 must be left floating.
If a crystal is attached, it requires external load capacitors to GND on each terminal of the
crystal. For details, see
If at any time the system wants to stop the clock on XTAL1, the link must first put the
ISP1505 into low-power mode. The clock on XTAL1 must be restarted before low-power
mode is exited.
This pin provides two optional functions. If neither function is used, this pin must be
connected to V
An active LOW asynchronous reset pin that resets all circuits in the ISP1505. The
ISP1505 contains an internal power-on reset circuit, and therefore using the RESET_N
pin is optional. If RESET_N is not used, it must be connected to V
For details on using RESET_N, see
PSW_N is an active LOW, open-drain output pin. This pin can be connected to an active
LOW, external V
power source. An external pull-up resistor, R
pin is open-drain, allowing ganged-mode power control for multiple USB ports. For
application details, see
To use the PSW_N pin, the link must disable the reset input by setting the
IGNORE_RESET bit in the Power Control register to logic 1. This will ensure that PSW_N
is not misinterpreted as a reset.
•
•
•
Set the USE_EXT_VBUS_IND register bit to logic 1.
Set the polarity of the external fault signal using the IND_COMPL register bit.
Set the IND_PASSTHRU register bit to logic 1.
CC(I/O)
BUS
switch or charge pump enable circuit to control the external V
.
Rev. 01 — 19 October 2006
Section
Section
16.
16.
Section
ULPI HS USB host and peripheral transceiver
9.3.2.
pullup
ISP1505A; ISP1505C
, is required when PSW_N is used. This
Section
16.
CC(I/O)
© NXP B.V. 2006. All rights reserved.
.
BUS
11 of 78