isp1505a NXP Semiconductors, isp1505a Datasheet - Page 12

• Manufacturer Part Number: isp1505a
• Description: Isp1505a; Isp1505c Ulpi Hi-speed Universal Serial Bus Host And Peripheral Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1505A_ISP1505C_1
Product data sheet
7.10.10 DIR
7.10.11 STP
7.10.12 NXT
7.10.13 CLOCK
If the link is in host mode, it can enable the external V
DRV_VBUS_EXT bit in the OTG Control register to logic 1. The ISP1505 will drive
PSW_N to LOW to enable the external V
overcurrent condition (the V
V
ULPI direction output pin. Controls the direction of the data bus. By default, the ISP1505
holds DIR at LOW, causing the data bus to be an input. When DIR is LOW, the ISP1505
listens for data from the link. The ISP1505 pulls DIR to HIGH only when it has data to
send to the link, which is for one of two reasons:
For details on DIR usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 .
ULPI stop input pin. The link must assert STP to signal the end of a USB transmit packet
or a register write operation. When DIR is asserted, the link can optionally assert STP to
abort the ISP1505, causing it to de-assert DIR in the next clock cycle. A weak pull-up
resistor is incorporated into the STP pin as part of the interface protect feature. For details,
see
For details on STP usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 .
ULPI next data output pin. The ISP1505 holds NXT at LOW by default. When DIR is LOW
and the link is sending data to the ISP1505, NXT will be asserted to notify the link to
provide the next data byte. When DIR is at HIGH and the ISP1505 is sending data to the
link, NXT will be asserted to notify the link that another valid byte is on the bus. NXT is not
used for the register read data or the RXCMD status update.
For details on NXT usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 .
A 60 MHz interface clock to synchronize the ULPI bus. CLOCK can be configured as input
or output. The ISP1505 provides three clocking options:
For details on CLOCK usage, refer to UTMI+ Low Pin Interface (ULPI) Specification
Rev. 1.1 .
BUS
•
•
•
•
•
To send the USB receive data, RXCMD status updates and register read data to the
link.
To block the link from driving the data bus during power-up, reset and low-power
mode (suspend).
A crystal attached between the XTAL1 and XTAL2 pins.
A clock driven into the XTAL1 pin, with the XTAL2 pin left floating.
A 60 MHz clock driven into the CLOCK pin, with XTAL1 tied to REG1V8 and XTAL2
left floating.
Section
supply by setting DRV_VBUS_EXT to logic 0.
9.3.1.
Rev. 01 — 19 October 2006
BUS
state in RXCMD is not 11b), it must disable the external
ULPI HS USB host and peripheral transceiver
BUS
power source. If the link detects an
ISP1505A; ISP1505C
BUS
power source by setting the
© NXP B.V. 2006. All rights reserved.
12 of 78