isp1505a NXP Semiconductors, isp1505a Datasheet - Page 20

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isp1505a

Manufacturer Part Number
isp1505a
Description
Isp1505a; Isp1505c Ulpi Hi-speed Universal Serial Bus Host And Peripheral Transceiver
Manufacturer
NXP Semiconductors
Datasheet

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ISP1505A_ISP1505C_1
Product data sheet
completed. After every reset, an RXCMD is sent to the link to update USB status
information. After this sequence, the ULPI bus is ready for use and the link can start USB
operations.
If a crystal is attached or a clock is driven into the XTAL1 pin, the ISP1505 will drive a
60 MHz clock out from the CLOCK pin when DIR de-asserts. This is shown as CLOCK
(output) in
pin, DIR will de-assert when internal clocks have synchronized. This is shown as CLOCK
(input) in
The recommended power-up sequence for the link is as follows:
The link waits for 1 ms, ignoring all the ULPI pin status.
The link may start to detect DIR status level. If DIR is detected as LOW for three clock
cycles, the link may send a RESET command.
The ULPI interface is ready for use.
Figure
Figure
4.
4. If no crystal is attached and a 60 MHz clock is driven into the CLOCK
Rev. 01 — 19 October 2006
ULPI HS USB host and peripheral transceiver
ISP1505A; ISP1505C
© NXP B.V. 2006. All rights reserved.
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