adav802 Analog Devices, Inc., adav802 Datasheet - Page 38

• Manufacturer Part Number: adav802
• Description: Audio Codec For Recordable Dvd
• Manufacturer: Analog Devices, Inc.

ADAV802
Table 51. Sample Rate Converter Error Mask Register
ADDRESS = 0011011
OVRL Mask
OVRR Mask
MUTE_IND MASK
Table 52. Interrupt Status Register
ADDRESS = 0011100
SRCERROR
TxCSTINT
TxUBINT
TxCSINT
RxCSDIFF
RxUBINT
RxCSBINT
RxERROR
SRC
Error
7
This bit will be set if one of the sample rate converter interrupts is asserted, and the host should immediately read the
Sample Rate Converter Error register. This bit will remain high until the Interrupt Status register is read
This bit will be set if a write to the transmitter channel status buffer was made while transmitter channel status bits were
being copied from transmitter CS buffer to SPDIF Transmit buffer
This bit will be set if the SPDIF Transmit buffer is empty. This bit will remain high until the Interrupt Status register is read.
This bit will be set if the transmitter channel status bit buffer has transmitted its block of channel status. This bit will remain
high until the Interrupt Status register is read
This bit will be set if the receiver Channel Status A block is different from the receiver Channel Status B clock. This bit will
remain high until read but does not generate an interupt
This bit will be set if the Receiver User bit buffer has a new block or message. This bit will remain high until the Interrupt
Status register is read.
This bit will be set if a new block of channel status is read when RxBCONF3 = 0 or if the channel status has changed when
RxBCONF3 = 1. This bit will remain high until the Interrupt Status register is read.
This bit will be set if one of the AES3/SPDIF receiver interrupts is asserted and the host should immediately read the Receiver
Error register. This bit will remain high until the Interrupt Status register is read.
RES
7
Masks the OVRL from generating an interrupt
0 = The OVRL bit will not generate an interrupt
1 = The OVRL bit will generate an interrupt
Masks the OVRR from generating an interrupt
0 = The OVRR bit will not generate an interrupt
1 = The OVRR bit will generate an interrupt Reserved
Masks the MUTE_IND from generating an interrupt
0 = The MUTE_IND bit will not generate an interrupt
1 = The MUTE_IND bit will generate an interrupt
TxCST-
INT
6
RES
6
RES
5
TxUB-
INT
5
RES
4
Rev. Pr G | Page 38 of 53
TxCS-
INT
4
RES
3
RxCS-
DIFF
3
OVRL Mask
2
RxUB-
INT
2
Preliminary Technical Data
OVRR Mask
1
RxCS-
BINT
1
MUTE_IND MASK
0
Rx-
ERROR
0