adav802 Analog Devices, Inc., adav802 Datasheet - Page 25

• Manufacturer Part Number: adav802
• Description: Audio Codec For Recordable Dvd
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Table 25. ZEROL/INT Pin Functionality
INTRPT
0
1
SERIAL DATA PORTS
The ADAV802 contains four flexible serial ports (SPORTs) to
allow data transfer to and from the codec. All four SPORTs are
independent and can be configured as master or slave ports. In
Slave Mode the xLRCLK and xBCLK signals are inputs to the
serial ports. In Master Mode, the serial port generates the
xLRCLK and xBCLK signals. The master clock for the SPORT
can be selected from a number of sources, as shown in Figure 34
and care should be taken to ensure that the clock rate is
appropriate for whatever block is connected to the serial port.
For example if the ADC is running from the MCLKI input at
256 × f
run from the MCLKI input to ensure that the ADC and serial
port are synchronised.
receive data in I
different word lengths by programming the appropriate bits in
the Playback, Auxiliary Input Port, Record and Auxiliary Output
Port Control Registers. Figure 33 shows a timing diagram of the
serial data port formats.
LRCLK
SDATA
LRCLK
SDATA
LRCLK
SDATA
BCLK
BCLK
BCLK
S
then the master clock for the SPORT should also run
MSB
Pin Functionality
The pin functions as a ZEROL flag pin
The pin functions as an interrupt pin
2
S, Left Justified or Right Justified formats with
.
MSB
The SPORTs can be set to transmit or
MSB
LEFT CHANNEL
LEFT CHANNEL
LEFT CHANNEL
RIGHT-JUSTIFIED MODE - SELECT NUMBER OF BITS PER CHANNEL
LEFT-JUSTIFIED MODE - 16 BITS TO 24 BITS PER CHANNEL
LSB
I
2
S MODE - 16 BITS TO 24 BITS PER CHANNEL
LSB
Rev. Pr G | Page 25 of 53
LSB
MSB
CLOCKING SCHEME
The ADAV802 provides a flexible choice of on-chip and off-
chip clocking sources. The on-chip oscillator with dual-PLLs is
intended to offer complete system clocking requirements for
use with available MPEG encoders, decoders or combination
codecs. The oscillator function is designed for generation of a
27 MHz video clock from a 27 MHz crystal connected between
XIN and XOUT pins. Capacitors are also required to be
connected between these pins and DGND as shown in Figure
15. The capacitor values should be specified by the crystal
manufacturer. A square-wave version of the crystal clock is
output on the MCLKO pin. If the system has 27MHz clock
available this can be connected directly to the XIN pin.
DATA PATH
The ADAV802 features a Digital Input/Output
switching/multiplexing matrix which gives flexibility to the
range of possible Input and Output connections. Digital Input
ports include Playback and Auxiliary Input - both 3-wire digital
- and S/PDIF (single wire to the on-chip receiver). Output ports
include the Record and Auxiliary Output ports - both 3-wire
digital - and the S/PDIF port (single wire from the on-chip
transmitter). Internally the DIR and DIT are interfaced via 3-
wire interfaces. The data path for each input and output port is
selected by programming Datapath Control Registers 1 and 2.
Figure 35 shows the internal data path structure of the
ADAV802.
MSB
MSB
RIGHT CHANNEL
RIGHT CHANNEL
RIGHT CHANNEL
Figure 33. Serial Data Modes
LSB
LSB
LSB
ADAV802