adav802 Analog Devices, Inc., adav802 Datasheet - Page 20

• Manufacturer Part Number: adav802
• Description: Audio Codec For Recordable Dvd
• Manufacturer: Analog Devices, Inc.

ADAV802
SPDIF TRANSMITTER AND RECEIVER
The ADAV802 contains an integrated SPDIF transmitter and
receiver. The transmitter consists of a single output pin,
DITOUT, on which the biphase encoded data appears. The
SPDIF transmitter source can be selected from the different
blocks making up the ADAV802. Additionally the clock source
for the SPDIF transmitter can be selected from the various clock
sources available in the ADAV802. The receiver uses two pins,
DIRIN and DIR_LF. DIRIN accepts the SPDIF input data
stream. The DIRIN pin can be configured to accept a digital
input level as defined by Table 13 or an input signal with a peak
to peak level of 200mV minimum as defined by the IEC60958-3
specification. DIR_LF is a loop filter pin required by the
internal PLL which is used to recover the clock from the SPDIF
data stream. The components shown in Figure 22 form a loop
filter which integrates the current pulses from a charge pump
and produces a voltage which is used to tune the VCO of the
clock recovery PLL. The recovered audio data and audio clock
can be routed to the different blocks of the ADAV801 as
required. Figure 19 shows a conceptual diagram of the DIRIN
block.
SPDIF
C
1
1 External Capacitor is only required for variable level SPDIF inputs
DIRIN
LEVEL
DC
REG: 0x74
BIT 4
COMPARATOR
Figure 19. DIRIN Block
44.1 kHz
44.1 kHz
48 kHz
32 kHz
48 kHz
32 kHz
256
384
256
384
256
512
RECEIVER
SPDIF
PLL2 MCLK
PLL1 MCLK
REG: 0x75
BITS 3-2
REG: 0x75
BIT 1
REG: 0x75
BIT 5
REG: 0x75
BITS 7-6
REG: 0x74
BIT 0
801-0128
Figure 18. PLL Clocking Scheme
Rev. Pr G | Page 20 of 53
REG: 0x75
BIT 0
REG: 0x75
BIT 4
×2
×2
FS3
FS2
FS1
/2
/2
/2
REG: 0x77
BIT 0
AUXILIARY IN
REG: 0x77
BITS 2-1
PLAYBACK
Figure 20. Digital Output Transmitter Block Diagram
Figure 21. Digital Input Receiver Block Diagram
ADC
SRC
PLLINT2
DIR
PLLINT1
PLL1
PLL2
801-0016
REG: 0x63
BITS 2-0
DIRIN
Preliminary Technical Data
DIR
SYSCLK3
SYSCLK1
SYSCLK2
DIT
INPUT
801-0022
DIT
Audio
Data
Recovered
Clock
DITOUT