adav802 Analog Devices, Inc., adav802 Datasheet
adav802
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adav802 Summary of contents
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... DVD-Recordable All Formats CD-R/W PRODUCT OVERVIEW The ADAV802 is a stereo audio codec intended for applications, such as DVD or CD recorders, requiring high performance, flexible and cost effective playback and record functionality. The ADAV802 features Analog Devices proprietary, high performance converter cores to provide record (ADC), playback (DAC) and format conversion (SRC single chip ...
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... ADAV802 TABLE OF CONTENTS Specifications..................................................................................... 3 Timing Specifications....................................................................... 7 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Functional Description .................................................................. 12 ADC Section ............................................................................... 12 DAC Section.................................................................................... 15 SRC Functional Overview ............................................................. 16 Theory of Operation .................................................................. 16 Conceptual High Interpolation Model.................................... 16 REVISION HISTORY Preliminary Technical Data Hardware Model......................................................................... 17 The Sample Rate Converter Architecture ............................... 17 PLL Section ...
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... Min Typ Max 100 99 102 −85 1.0 1.5 −1 0.01 100 TBD 100 0.39 -48 TBD Rev Page ADAV802 +3.3 V +3.3 V 25°C 12.288 MHz kHz 24-bits 100 pF 997Hz at −1 dBFS 997Hz at −1 dBFS Unit Conditions kΩ Unit Conditions V ° ppm/ ...
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... ADAV802 Table 5. ADC Low-Pass Digital Decmation Filter Characteristics Sample Rate Pass Band (kHz) Frequency (kHz) 48 0.45314 × TBD × Guaranteed by Design Table 6. ADC High-Pass Digital Filter Characteristics (f Cutoff Frequency Table 7. SRC Section Resolution Sample Rate Maximum Sample Rate Ratios ...
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... TBD TBD TBD Min Typ Max 27.2 220 Min Typ Max 2.0 DVDD 0 2.4 0.4 15 Rev Page ADAV802 Pass Band Ripple (dB) ±0.002 ±0.002 ±0.005 Unit Conditions MHz MHz × f 256/384/512/768 × 32/44.1/48 kHz × f 256/384/512/768 × 32/44.1/48 kHz × f 256/512 × ...
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... ADAV802 Table 14. Power Supplies Voltage, AVDD Voltage, DVDD Voltage, ODVDD Analog Current Digital Current, DVDD Digital Interface Current, ODVDD Analog Current—Power Down Digital Current - Power Down Digital Interface Current - Power Down Power Supply Rejection 1 kHz 300 mV Signal at Analog Supply Pins ...
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... Min Typ 25 −40 −65 Rev Page ADAV802 Comments Relevant for Repeated Start Condition After this period the 1st clock is generated To xBCLK Rising Edge From xBCLK Rising Edge To xBCLK Rising Edge From xBCLK Rising Edge From xBCLK Falling Edge ...
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... ADAV802 ABSOLUTE MAXIMUM RATINGS Table 17. Parameter Rating DVDD to DGND and ODVDD 4 DGND AVDD to AGND 4.6 V Digital Inputs DGND − 0 DVDD + 0.3 V Analog Inputs AGND − 0 AVDD + 0.3 V AGND to DGND −0 +0.3 V Reference Voltage Indefinite short circuit to ground Soldering (10 s) +300° ...
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... Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DIR_GND DIR_VDD CLATCH/AD0 CCLK/SCL COUT/AD1 ZEROL/INT Table 18. ADAV802 Pin Function Descriptions Pin Number Input/Output Mnemonic 1 INPUT VINR 2 INPUT VINL 3 AGND 4 AVDD 5 DIR_LF 6 DIR_GND 7 DIR_VDD 8 INPUT RESET 9 INPUT CLATCH 10 INPUT CIN 11 INPUT CCLK 12 OUTPUT ...
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... ADAV802 Pin Number Input/Output Mnemonic 23 INPUT DIRIN 24 ODVDD 25 ODGND 26 OUTPUT DITOUT 27 INPUT/OUTPUT OAUXLRCLK 28 INPUT/OUTPUT OAUXBCLK 29 OUTPUT OAUXSDATA 30 INPUT/OUTPUT IAUXLRCLK 31 INPUT/OUTPUT IAUXBCLK 32 INPUT IAUXSDATA 33 DGND 34 DVDD 35 INPUT MCLKI 36 OUTPUT MCLKO 37 INPUT XOUT 38 INPUT XIN 39 OUTPUT SYSCLK3 40 OUTPUT SYSCLK2 41 OUTPUT SYSCLK1 42 DGND 43 PLL_VDD ...
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... Preliminary Technical Data (continued from Page 1) Operation of the ADAV802 is controlled via an SPI compatible serial interface which allows individual Control Register settings to be programmed. The ADAV802 operates from a single analog +3.3 V power supply - and a digital power supply of +3.3 V with optional digital interface range of 3 +3.6 V. ...
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... ADAV802 FUNCTIONAL DESCRIPTION ADC SECTION The ADAV802's ADC section is implemented using a 2 multi-bit (5-bits) Sigma-Delta modulator. The modulator is sampled at either half the ADC MCLK rate (Modulator Clock = 128 × quarter of the ADC MCLK rate (Modulator Clock × The digital decimator consists of a Sinc^5 filter S followed by a cascade of 3 half-band FIR filters ...
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... Attack Threshold and the ALC then enters Attack Mode. Care should be exercised when using this mode to choose values for the Attack and Recovery thresholds to prevent excessive volume modulation caused by continuous gain adjustments. Limited Recovery Limited Recovery Mode offers a compromise between No Rev Page ADAV802 ...
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... ADAV802 Recovery and Normal Recovery Modes. If the output level of the ADC exceeds the Attack Threshold then Attack Mode is initiated. When Attack Mode has reduced the PGA gain to suitable levels the ALC will attempt to recovery the gain to its original level. If the ADC output level exceeds the level set by the Recovery Threshold bits a counter is incremented (GAINCNTR) ...
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... Preliminary Technical Data DAC SECTION The ADAV802 has two DAC channels arranged as a stereo pair with differential analog outputs. Each channel has its own independently programmable attenuator, adjustable in 128 steps of 0.375dB per step. The DAC can receive data from the playback or auxiliary input ports, the SRC, the ADC or the DIR. ...
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... Since the ratio irrational number, the error resulting from the re- sampling at fS_OUT can never be eliminated. However, the error can be significantly reduced through interpolation of the input data at fS_IN. The sample rate converter in the ADAV802 is conceptually interpolated by a factor of 2 ZERO-ORDER IN ...
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... SERVO LOOP SAMPLE RATE RATIO FIR FILTER f S_IN SAMPLE RATE RATIO f S_OUT EXTERNAL RATIO Figure 12. Architecture of the Sample Rate Converter /f ) when f < The FIFO also scales the input S_IN S_OUT S_IN ADAV802 sample rates HIGH ORDER INTERP L/R DATA OUT 801-0011 S_IN ...
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... The FIR S_IN S_OUT Figure 14. Frequency Response of the Digital Servo Loop. fS_IN is the X-Axis, period. The FIR S_OUT PLL SECTION The ADAV802 features a dual PLL configuration to generate for f ≥ independent system clocks for asynchronous operation. Figure S_OUT S_OUT 17 shows the block diagram of the PLL section. The PLL generates the internal and system clocks from a 27MHz clock ...
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... PLL1 and PLL2 are selected. The clock nodes, PLL1 and PLL2, can be used as master clocks for the other blocks in the ADAV802 such as the DAC or ADC. The PLL has separate supply and ground pins and these should be as clean as possible to prevent electrical noise being converted into clock jitter by coupling onto the loop filter pins ...
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... ADAV802. Additionally the clock source for the SPDIF transmitter can be selected from the various clock sources available in the ADAV802. The receiver uses two pins, DIRIN and DIR_LF. DIRIN accepts the SPDIF input data stream. The DIRIN pin can be configured to accept a digital ...
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... DIR_LF Figure 22. DIR loop Filter Components Serial Digital Audio Transmission Standards The ADAV802 can receive and transmit SPDIF, AES/EBU and IEC-958 serial streams. SPDIF is a consumer audio standard and AES/EBU is a professional audio standard. IEC-958 has both consumer and professional definitions. This data sheet is ...
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... Receiver Section The ADAV802 uses a double buffering scheme to handle Non- Pro/Con Audio =1 reading Channel Status and User bit information. The Channel Channel Mode ...
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... BCONF3 bit. If the bit is 0 the user bits will begin transmitting straight away without alignment to the Z preamble. If this bit is 1 the User bits will not start transmitting until a Z preamble occurs when the TxBCONF2-1 bits are 01. Rev Page ADAV802 DITOUT CHANNEL STATUS A ( BITS) ...
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... Autobuffer register enables zeros to be added or subtracted between messages. Interrupts SPDIF OUT The ADAV802 provides interrupt bits to indicate the presence of certain conditions which may require attention. Reading the Interrupt Status register will allow the user to determine if any 0.....7 of the interrupts have be asserted. The bits of the Interrupt 8 ...
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... BCLK MSB SDATA CLOCKING SCHEME The ADAV802 provides a flexible choice of on-chip and off- chip clocking sources. The on-chip oscillator with dual-PLLs is intended to offer complete system clocking requirements for use with available MPEG encoders, decoders or combination codecs. The oscillator function is designed for generation MHz video clock from a 27 MHz crystal connected between XIN and XOUT pins ...
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... The SPI control port wire serial control port with one cycle of data transfer consisting of 16 bits. Figure 36 shows the format of an SPI write/read of the ADAV802. The transfer of data is initiated on the falling edge of CLATCH. The data presented on the first 7 CCLKs represents the register address required to be written to or read from ...
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... Block Reads and Writes The ADAV802 provides the user with the ability to write to or read from a block of registers in one continuous operation. In SPI mode, the CLATCH line should be held low for longer than the 16 CCLK periods to use the block read/write mode. For a ...
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... ADAV802 Table 26. SRC & Clock Control Register SRCDIV1 7 ADDRESS = 0000000 SRCDIV1-0 Divides the SRC Master Clock 00 = The SRC Master Clock is not divided 01 = The SRC Master Clock is divided by 1 The SRC Master Clock is divided by 2 11= The SRC Master Clock is divided by 3 CLK2DIV1-0 ...
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... Bit Right Justified 101 = 20 Bit Right Justified 110 = 18 Bit Right Justified 111 = 16 Bit Right Justified RES RES CLKSRC1 CLKSRC0 RES RES CLKSRC1 CLKSRC0 Rev Page ADAV802 SPMODE2 SPMODE1 SPMODE0 SPMODE2 SPMODE1 SPMODE0 ...
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... ADAV802 Table 30. Record Port Control Register RES RES 7 6 ADDRESS = 0000110 RES Reserved CLKSRC1-0 Selects the Clock Source for generating the OLRCLK and OBCLK 00 = Record Port is a Slave 01 = Recovered PLL Clock 10 = Internal Clock Internal Clock 2 WLEN1-0 Selects the Serial Output Word Length ...
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... Adds delay to the Sample Rate Converter FIR filter by GRPDLY6-0 Input Samples 0000000 = No Delay 0000001 = 1 Sample Delay 0000010 = 2 Sample Delay 1111110 = 126 Sample Delay 1111111 = 127 Sample Delay RXCLK1-0 AUTO_ DEEMPH 6,5 4 recovered clock S recovered clock S recovered clock S Rev Page GRPDLY6-0 6,5,4,3,2,1,0 ERR1-0 LOCK1-0 3,2 1,0 ADAV802 ...
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... ADAV802 Table 34. Receiver Configuration 2 Register RxMUTE 7 ADDRESS = 0001010 RxMUTE Hard Mutes the Audio Output for the AES3/SPDIF Receiver 0 = AES3/SPDIF Receiver is not muted 1 = AES3/SPDIF Receiver is muted The AES3/SPDIF Receiver PLL will accept a Left/Right Clock from one of the four serial ports as the PLL ...
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... Reserved TxBCONF0 Determines the buffer size of the transmitter user bits when TxBCONF2 384 Bits with Preamble-Z as the start of the buffer 1 = 768 Bits with Preamble-Z as the start of the buffer Tx-RATIO2-0 TxCLK SEL1-0 5,4,3 2,1 TxBCONF3 TxBCONF2-1 3 2,1 Rev Page ADAV802 Tx-ENABLE 0 TxBCONF0 0 ...
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... ADAV802 Table 38. Channel Status Switch Buffer and Transmitter RES RES 7 6 ADDRESS = 0001110 Tx_A/B_Same Transmitter Channel Status A and B are the same. The transmitter will only read from the Channel Status A buffer and place the data into the Channel Status B buffer 0 = Channel Status for A and B are separate ...
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... The eight least significant bits of the sixteen bit Preamble-C when Nonaudio data is detected according to the PRE_C07-00 IEC60937 standard, otherwise bits show zeros Zero_Stuff_IU Auto_Ubits 6 5 SRCRATIO14-SRCRATIO08 6,5,4,3,2,1,0 SRCRATIO07-SRCRATIO01 7,6,5,4,3,2,1,0 The eight least significant bits of the fifteen bit sample rate ratio Rev Page ADAV802 Auto_CSBits IU_Zeros3-0 4 3,2,1,0 ...
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... ADAV802 Table 46. Preamble-D MSB Register (Read Only) PRE_D15-PRE_D08 7,6,5,4,3,2,1,0 ADDRESS = 0010110 PRE_D15-08 The eight most significant bits of the sixteen bit Preamble-D when Nonaudio data is detected according to the IEC60937 standard, otherwise bits show zeros. When subframe Nonaudio is used this becomes the 8 most significant bits of the 16 bit Preamble-C of Channel B Table 47 ...
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... SRC can be muted, if required, until the SRC is in Slow Mode. Once read this bit will remain in its state and not generate an interrupt until it has changed state. NonAudio Emphasis Nonaudio Preamble Mask Mask Mask RES RES TOO_SLOW Rev Page ADAV802 CRC BiPhase/ Error Nostream Parity Mask Mask Mask OVRL OVRR MUTE_IND Lock ...
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... ADAV802 Table 51. Sample Rate Converter Error Mask Register RES RES 7 6 ADDRESS = 0011011 Masks the OVRL from generating an interrupt OVRL Mask 0 = The OVRL bit will not generate an interrupt 1 = The OVRL bit will generate an interrupt OVRR Mask Masks the OVRR from generating an interrupt ...
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... Selects the Deemphasis Filter for the input data to the Sample Rate Converter Deemphasis kHz Deemphasis 10 = 44.1 kHz Deemphasis kHz Deemphasis TxUBINT TxCSBINT Mask Mask RES TxMUTE RES RES DEFAULT VALUE = 0x00 Rev Page ADAV802 RxUBINT RxCSBINT RxError Mask Mask Mask SRC_DEEM1-0 RES 2,1 0 ...
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... ADAV802 Table 55. NonAudio Preamble Type Register (Read Only) RES RES 7 6 ADDRESS = 0011111 DEFAULT VALUE = 0x DTS-CD Preamble Will be set if the DTS-CD Preamble is detect NonAudio Frame This bit will be set if the data received through the AES3/SPDIF Receiver is nonaudio data according to the IEC61937 standard or nonaudio data according to SMPTE337M ...
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... Absolute Absolute Absolute Minute Minute Minute Absolute Absolute Absolute Second Second Second Absolute Absolute Absolute Frame Frame Frame Rev Page ADAV802 QCRCERROR QSUB 1 0 BIT2 BIT1 BIT0 Control Control Control Track Track Track Number Number Number Index Index Index ...
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... ADAV802 Table 64. Datapath Control Register 1 SRC1 7 ADDRESS = 1100010 SRC1-0 Datapath Source Select for Sample Rate Converter(SRC ADC 01 = DIR 10 = Playback 11 = Auxiliary In REC2-0 Datapath Source Select for Record Output Port 000 = ADC 001 = DIR 010 = Playback 011 = Auxiliary In 100 = SRC AUXO2-0 Datapath Source Select for Auxiliary Output Port ...
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... Reserved DEEM1-0 DAC De-emphasis Select 00 = None 01 = 44.1 kHz kHz kHz DR_DIG CHSEL1 6 5 Level REF RES DMCLK1 DMCLK0 Rev Page CHSEL0 POL1 POL0 MUTER DFS DFS0 DEEM1 ADAV802 MUTEL 0 DEEM0 0 ...
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... ADAV802 Table 68. DAC Control Register 3 RES 7 ADDRESS = 1100110 ZFVOL DAC Zero Flag on Mute and Zero Volume 0 = Enabled 1 = Disabled DAC Zero Flag on Zero Data Disable ZFDATA 0 = Enabled 1 = Disabled ZFPOL DAC Zero Flag Polarity 0 = Active High 1 = Active Low Table 69. DAC Control Register 4 RES ...
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... DLP5 DLP4 RES DRP5 DRP4 RES AGL5 AGL4 RES AGR5 AGR4 Rev Page DLP3 DLP2 DLP1 DRP3 DRP2 DRP1 AGL3 AGL2 AGL1 AGL0 AGR3 AGR2 AGR1 ADAV802 DLP0 0 DRP0 0 AGR0 0 ...
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... ADAV802 Table 76. ADC Control Register 1 AMC 7 ADDRESS = 1101110 AMC ADC Modulator Clock 0 = ADC MCLK/2 (128 × ADC MCLK/4 (64 × f High Pass Filter Enable HPF 0 = Normal 1 = HPF Enabled PWRDWN ADC Powerdown 0 = Normal 1 = Powerdown ADC Analog Section Powedown ANA_PD 0 = Normal 1 = Powedown MUTER ...
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... S AVOLR5 AVOLR4 AVOLR3 ALP5 ALP4 ALP3 RES ARP5 ARP4 ARP3 MCLKODIV PLLDIV PLL2PD Rev Page ADAV802 AVOLR2 AVOLR1 AVOLR0 ALP2 ALP1 ALP0 ARP2 ARP1 ARP0 PLL1PD XTLPD SYSCLK3 ...
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... ADAV802 Table 83. PLL Control Register 2 FS2-1 FS2 ADDRESS = 1110101 FS2_1-0 Sample Rate Select for PLL2 kHz 01 = Reserved kHz 11 = 44.1 kHz SEL2 Oversample Ratio Select for PLL2 0 = 256 × 384 × DOUB2 Double Selected Sample Rate on PLL2 0 = Disabled ...
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... DIR PLL (512 × 101 = DIR PLL (256 × 110 = XIN 111 = XIN Source Selector for Internal Clock ICLK2 ICLK2 00 = XIN 01 = MCLKI 10 = PLLINT1 11 = PLLINT2 DCLK1 DCLK0 ACLK2 ACLK1 Rev Page ADAV802 ACLK0 ICLK2-1 ICLK2 ...
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... ADAV802 Table 85. Internal Clocking Control Register 2 RES 7 ADDRESS = 1110111 ICLK1-0 Source Selector for Internal Clock ICLK1 00 = XIN 01 = MCLKI 10 = PLLINT1 11 = PLLINT2 PLL2INT1-0 PLL2 Internal Selector (See Figure 18 FS2 01 = FS2 FS3 11 = FS3/2 PLL1INT PLL1 Internal Selector 0 = FS1 1 = FS1/2 Table 86. PLL Clock Source Register ...
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... RECTIME1-0 Recovery Time Selection 128 256 ms ATKTIME Attack Timer Selection GAINCNTR1-0 RECMODE1-0 5,4 3,2 Default = 0x00 RECTH1-0 6,5 Default = 0x52 Rev Page ADAV802 LIMDET ALCEN 1 0 ATKTH1-0 RECTIME1-0 ATKTIME 4,3 2,1 0 ...
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... ADAV802 Table 90. ALC Control Register 3 ALC RESET 7,6,5,4,3,2,1,0 ADDRESS = 1111101 Default = 0x00 ALC RESET A write to this register will restart the ALC operation. The value written to this register is irrelevant. A read from this register will give the gain reduction factor. Preliminary Technical Data Rev Page ...
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... Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR04757-0-3/04(PrG) Figure 41. 64-Lead Plastic Quad Flatpack [LQFP] (ST-64) Dimensions shown in inches and (millimeters) Control Interface SPI Rev Page ADAV802 DAC Outputs Package Options Differential ST-64 ...