adav802 Analog Devices, Inc., adav802 Datasheet - Page 22

• Manufacturer Part Number: adav802
• Description: Audio Codec For Recordable Dvd
• Manufacturer: Analog Devices, Inc.

ADAV802
The standards allow for the channel status bits in each subframe
to be independent, but ordinarily the channel status bit in the
two subframes of each frame are the same. The channel status
bits are defined differently for the consumer audio standards
and the professional audio standards. The 192 channel status
bits are organized into 24 bytes and have the interpretations
shown in Figure 27 and Figure 28.
The SPDIF transmitter and receiver have a comprehensive
register set. The registers give the user full access to the
functions of the SPDIF block such as detecting non-audio and
validity bits, Q subcodes, preambles etc. The channel status bits
as defined by the IEC60958 and AES3 specification are stored in
register buffers for ease of use. An autobuffering function allows
for channel status and user bits read by the receiver to be copied
directly to the transmitter block removing the need for user
intervention.
N = 0x20 for Receiver Channel Status Buffer
N = 0x38 for Transmitter Channel Status Buffer
Address
N+10
N+11
N+12
N+13
N+14
N+15
N+16
N+17
N+18
N+19
N+20
N+21
N+22
N+23
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N
Scaling
Frequency
Alignment
7
Sample
fs
Level
Alphanumeric Channel Destination Data - First Character
User Bit Management
Alphanumeric Channel Destination Data - Last Character
Reliability Flags
Alphanumeric Channel Origin Data - First Character
Alphanumeric Channel Origin Data - Last Character
6
Cyclic Redundancy Check Character (CRCC_
Sample Frequency (fs)
Alphanumeric Channel Destination Data
Alphanumeric Channel Destination Data
Local Sample Address Code - MSW
Figure 28. Professional
Alphanumeric Channel Origin Data
Local Sample Address Code - LSW
Alphanumeric Channel Origin Data
Lock
Source Word Length
5
Local Sample Address Code
Local Sample Address Code
Time Of Day Code - MSW
Time Of Day Code - LSW
Channel Identification
Time Of Day Code
Time Of Day Code
4
Data Bits
Reserved
Emphasis
3
erved
Res-
Channel Mode
Use of Auxiliary Mode
2
Reserved
Sample Bits
Reference Signal
Audio
Non-
Digital Audio
1
Pro/Con
=1
0
Rev. Pr G | Page 22 of 53
Receiver Section
The ADAV802 uses a double buffering scheme to handle
reading Channel Status and User bit information. The Channel
Status bits are available as a memory buffer taking up 24
consecutive register locations. The User bits are read using an
indirect memory addressing scheme where the Receiver User
Bit Indirect Address register is programmed with an offset to
the User bit buffer and the Receiver User Bit Data register can
be read to determine the User bits at that location. Reading the
Receiver User Bit Data register automatically updates the
Indirect Address Register to the next location in the buffer.
Typically the Receiver User Bit Indirect Address register is
programmed to zero, the start of the buffer, and the Receiver
User Bit Data register is read repeatedly until all the buffers data
has been read. Figure 29 and Figure 30 shows how receiving the
Channel Status and User bits is implemented.
The SPDIF receive buffer is updated continuously by the
incoming SPDIF stream and once all of the channel status bits
for the block, 192 for channel A and 192 for channel B, are
received the bits are copied into the receiver channel status
buffer. This buffer stores all 384 bits of channel status
information and the RxCSSWITCH bit in the Channel Status
Switch Buffer register determines whether the channel A or
channel B status bits are required to be read. The receive
channel status bit buffer is 24 bytes long and spans the address
range from 0x20 to 0x37.
Since the Channel Status bits of an SPDIF stream rarely change
a software interrupt/flag bit, RxCSBINT is provided to notify
the host control that either a new block of channel status bits is
available or that the first 5 bytes of channel status information
SPDIF IN
BUFFER
16.....23
8.....15
FIRST
0.....7
FIRST BUFFER
RECEIVE
BUFFER
DIRIN
SPDIF
Figure 30. Receiver User Bit Buffer
Figure 29. Channel Status Buffer
USER BIT
BUFFER
16.....23
Preliminary Technical Data
8.....15
0.....7
(24 X 8 BITS)
(24 X 8 BITS)
STATUS A
STATUS B
CHANNEL
CHANNEL
ADDRESS = 0x51
ADDRESS = 0x50
RECEIVER USER BIT
INDIRECT ADDRESS
RECEIVER USER BIT
DATA REGISTER
SECOND BUFFER
REGISTER
RxCSSWITCH
CS BUFFER
(0x20-0x37)
RECEIVE
801-0032