adav802 Analog Devices, Inc., adav802 Datasheet - Page 26

• Manufacturer Part Number: adav802
• Description: Audio Codec For Recordable Dvd
• Manufacturer: Analog Devices, Inc.

ADAV802
INTERFACE CONTROL
The ADAV802 has a dedicated control port to allow the internal
registers of the ADAV802 to be accessed. Each of the internal
registers is 8 bits wide. Where bits are described as reserved
(RES) these bits should be programmed as zero.
SPI Interface
Control of the ADAV802 is via an SPI compatible serial port.
The SPI control port is a 4 wire serial control port with one
cycle of data transfer consisting of 16 bits. Figure 36 shows the
format of an SPI write/read of the ADAV802. The transfer of
data is initiated on the falling edge of CLATCH. The data
presented on the first 7 CCLKs represents the register address
required to be written to or read from. The 8th bit of data is a
DIR PLL (256 × f S )
DIR PLL (512 × f S )
DIR PLL (256 × f S )
DIR PLL (512 × f S )
REFERENCE
ADC
DAC
PLLINT1
PLLINT2
PLLINT1
PLLINT2
PLL
MCLKI
MCLKI
PLLINT1
PLLINT2
PLLINT1
PLLINT2
MCLKI
MCLKI
REGISTERS
XIN
XIN
CONTROL
REG: 0x76
REG: 0x76
XIN
XIN
BITS 4-2
BITS 7-5
Figure 34. Sport Clocking Scheme
REG: 0x77
BITS 4-3
REG: 0x76
BITS 1-0
DIR PLL (512 × f S )
DIR PLL (256 × f S )
Rev. Pr G | Page 26 of 53
OSCILLATOR
MCLK
MCLK
ICLK1
ICLK2
PLL CLOCK
PLL CLOCK
Figure 35. Data Path
ADC
DAC
SRC
ICLK1
ICLK2
ICLK1
ICLK2
PLAYBACK
INPUT
DATA
REG: 0x00
BIT 1-0
OUTPUT
Read/Write bit. If this bit is low the following 8 bits of data will
be loaded to register address provided. If this bit is high a read
operation is indicated. The contents of the register address will
be clocked out on the COUT pin on the following 8 CCLKs. For
a read operation the data bits after the Read/Write bits are
ignored.
INPUT
PORT
PORT
INPUT
DATA
REG:0X04
BITS 4-3
AUX
REG:0x06
BITS 4-3
MCLK
SRC
DIR
RECORD
OUTPUT
OUTPUT
DATA
DATA
AUX
DIT
Preliminary Technical Data
OLRCLK
OBCLK
OSDATA
ILRCLK
IBCLK
ISDATA