ADV212 AD [Analog Devices], ADV212 Datasheet
ADV212
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ADV212 Summary of contents
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... The ADV212 is an upgrade version of the ADV202 that is identical in pinout and footprint. It supports all the functionality of the ADV202 and has the following additional options: • ...
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... Wavelet Engine ........................................................................... 25 Entropy Codecs........................................................................... 25 Embedded Processor System .................................................... 25 REVISION HISTORY 10/06—Revision 0: Initial Version Memory System.......................................................................... 25 Internal DMA Engine ................................................................ 25 ADV212 Interface .......................................................................... 26 Video Interface (VDATA Bus).................................................. 26 Host Interface (HDATA Bus) ................................................... 26 Direct and Indirect Registers .................................................... 26 Control Access Registers ........................................................... 27 Pin Configuration and Bus Sizes/Modes ................................ 27 Stage Register .............................................................................. 27 JDATA Mode ...
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... The ADV212 can process images at a rate of 40 MSPS in reversible mode and at higher rates when used in irreversible mode. The ADV212 contains a dedicated wavelet transform engine, three entropy codecs, an on-board memory system, and an embedded reduced instruction set computer (RISC) processor that can provide a complete JPEG 2000 compression/decompression solution ...
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... Dynamic Current, Core (JCLK Frequency = 150 MHz) Dynamic Current, Core (JCLK Frequency = 108 MHz) Dynamic Current, Core (JCLK Frequency = 81 MHz) Dynamic Current, Input/Output 1 No clock or input/output activity. 2 ADV212-150 only. INPUT/OUTPUT SPECIFICATIONS Table 2. Parameter High Level Input Voltage High Level Input Voltage Low Level Input Voltage ...
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... MCLK t 6 MCLKL t 6 MCLKH t 13.4 VCLK f 20 VCLK t 5 VCLKL t 5 VCLKH t 5 RESET t MCLK t t MCLKL MCLKH t VCLK t t VCLKL VCLKH Figure 2. Input Clock Rev Page Typ Max Unit 100 ns 75.18 MHz 74.60 MHz ns ns MCLK cycles ADV212 1 ...
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... ADV212 NORMAL HOST MODE—WRITE OPERATION Table 4. Parameter WE to ACK, Direct Registers and FIFO Accesses WE to ACK, Indirect Registers Data Setup Data Hold Address Setup Address Hold Setup CS Hold Write Inactive Pulse Width (Minimum Time Until Next WE Pulse) Write Active Pulse Width ...
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... JCLK RL t 5.0 JCLK RCYC RCYC ACK t t DRD HZRD VALID Figure 4. Normal Host Mode—Read Operation Rev Page ADV212 Typ Max 1.5 × JCLK + 7.0 15.5 × JCLK + 7.0 1.5 × JCLK + 7.0 15.5 × JCLK + 7.0 8.5 2 Unit ...
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... ADV212 DREQ/DACK DMA MODE—SINGLE FIFO WRITE OPERATION Table 6. Parameter DREQ Pulse Width DACK Assert to Subsequent DREQ Delay WE to DACK Setup Data to DACK Deassert Setup Data to DACK Deassert Hold DACK Assert Pulse Width DACK Deassert Pulse Width WE Hold After DACK Deassert WE Assert to FSRQ Deassert (FIFO Full) DACK to DREQ Deassert (DR × ...
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... HDATA Figure 7. Single Write Cycle for Fly-By DMA Mode ( DREQ Pulse Width Is Programmable) FCS0 RD FIFO NOT FULL FSRQ0 0 HDATA Figure 8. Single Write Access for DCS DMA Mode WFSRQ 1 Rev Page ADV212 t WEHD FIFO FULL 2 NOT WRITTEN TO FIFO ...
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... ADV212 DREQ/DACK DMA MODE—SINGLE FIFO READ OPERATION Table 7. Parameter DREQ Pulse Width DACK Assert to Subsequent DREQ Delay RD to DACK Setup DACK to Data Valid Data Hold DACK Assert Pulse Width DACK Deassert Pulse Width RD Hold after DACK Deassert RD Assert to FSRQ Deassert (FIFO Empty) DACK to DREQ Deassert (DR × ...
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... RDFB t RD HDATA 0 Figure 11. Single Read Cycle for Fly-By DMA Mode ( DREQ Pulse Width Is Programmable) FCS0 RD FIFO NOT EMPTY FSRQ0 HDATA Figure 12. Single Read Access for DCS DMA Mode RDFSRQ FIFO EMPTY 1 Rev Page ADV212 t RDHD ...
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... ADV212 EXTERNAL DMA MODE—FIFO WRITE, BURST MODE Table 8. Parameter 1 DREQ Pulse Width WE to DREQ Deassert (DR × PULS = 0) DACK to WE Setup Data Setup Data Hold WE Assert Pulse Width WE Deassert Pulse Width WEDeassert to Next DREQ WE Deassert to DACK Deassert 1 Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a nonzero value. ...
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... Programmed to a Value of 0000) t DREQRTN t DACKSU Figure 18. Burst Read Cycle for Fly-By DMA Mode Rev Page Typ Max 2 15 JCLK 3.5 × JCLK + 7.5 9.7 3.5 × JCLK + 7.5 t DREQWAIT t RD_DACK DREQWAIT t RD_DACK DREQWAIT t RD_DACK 14 15 ADV212 Unit ...
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... ADV212 STREAMING MODE (JDATA)—FIFO READ/WRITE Table 10. Parameter MCLK to JDATA Valid MCLK to VALID Assert/Deassert HOLD Setup to Rising MCLK HOLD Hold from Rising MCLK JDATA Setup to Rising MCLK JDATA Hold from Rising MCLK 1 For a definition of JCLK, see Figure 32. MCLK JDATA TD JDATA VALID ...
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... Figure 23. Encode Video Mode Timing—HVF Mode (VSYNC and FIELD Timing) Mnemonic VDATA VDATA VDATA HSYNC HSYNC HSYNC VSYNC VSYNC VSYNC FIELD FIELD FIELD SYNC DELAY ADV212 User Guide for more information. VDATA EAV FF 00 Figure 21. Encode Video Mode Timing—CCIR 656 Mode HSYNC Figure 22. Encode Video Mode Timing— ...
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... ADV212 VCLK VDATA TD VDATA (OUT) HSYNC (IN) VSYNC (IN) FIELD FIELD (IN) VCLK VDATA TD VDATA (OUT) HSYNC (IN) VSYNC (IN) FIELD FIELD (IN) VCLK VDATA (OUT) HSYNC (OUT) VSYNC (OUT) FIELD TD FIELD (OUT) Figure 26. Decode Video Mode Timing—CCIR 656 Mode, Decode Master VCLK VDATA (OUT) HSYNC (OUT) ...
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... RAW PIXEL MODE—DECODE Figure 28. Raw Pixel Modes Rev Page Mnemonic Min Typ VDATA TD VDATA 4 SU VDATA 4 HD VRDY TD VFRM 3 SU VFRM 4 HD VFRM TD VSTRB 4 SU VSTRB 3 HD VSTRB HD PIXEL 3 VSTRB HD ADV212 Max Unit ...
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... ADV212 JTAG TIMING Table 13. Parameter TCK Period TDI or TMS Setup Time TDI or TMS Hold Time TDO Hold Time TDO Valid TRST Hold Time TRST Setup Time TRST Pulse Width Low TCK TDO TDI TMS TRST Mnemonic Min TCK 134 TDI 4.0 SU TDI 4 ...
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... THERMAL RESISTANCE θ is specified for the worst-case conditions, that is, a device JA soldered in a circuit board for surface-mount packages. Table 15. Thermal Resistance Package Type 144-Ball ADV212BBCZ 121-Ball ADV212BBCZ ESD CAUTION Rev Page ADV212 θ θ Unit ...
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... ADV212 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS BOTTOM VIEW (Not to Scale) Figure 30.121-Ball Pin Configuration Rev Page BOTTOM VIEW (Not to Scale) Figure 31 ...
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... PLL_HI register, Bit 4, must be set to 1. Interrupt. This pin indicates that the ADV212 requires the attention of the host processor. This pin can be programmed to indicate the status of the internal interrupt conditions within the ADV212. The interrupt sources are enabled via the bits in register EIRQIE. ...
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... FIFO Chip Select. Used in DCS-DMA Mode. Chip select for the FIFO assigned to Channel 0 (asynchronous mode). Data Request for External DMA Interface. Indicates that the ADV212 is ready to send/receive data to/from the FIFO assigned to DMA Channel 1. FIFO Service Request. Used in DCS-DMA Mode. Service request from the FIFO assigned to Channel 1 (asynchronous mode) ...
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... Serial Communication. For internal use only. This pin should be tied low via a 10 kΩ resistor. Serial Communication. This pin must be used in multiple chip mode to align the outputs of two or more ADV212s. For details, see the Applications section and the AN-796 Application Note. When not used, this pin should be tied low via a 10 kΩ ...
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... K7 124, 129 In fly-by mode DMA, the function of the RD and WE signals (for DMA only) are reversed. This allows a host to move data between an external device and the ADV212 1 with the use of a single strobe encode mode with fly-by DMA, the host can use the RDFB signal ( WE pin) to simultaneously read from the ADV212 and write to an external device like memory. ...
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... THEORY OF OPERATION The input video or pixel data is passed on to the ADV212’s pixel interface, and samples are deinterleaved and passed on to the wavelet engine, which decomposes each tile or frame into subbands using the 5/3 or 9/7 filters. The resultant wavelet coefficients are then written to the internal memory. The entropy codecs code the image data so that it conforms to the JPEG 2000 standard ...
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... The default bus mode uses the same pins to transfer control, status, and data to and from the ADV212. In this mode, the ADV212 can support 16- and 32-bit control transfers and 8-/16-/32-bit data transfers. The size of these buses can be selected ...
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... A 2-pin handshake is used to transfer data over this synchronous interface. VALID is used to indicate that the ADV212 is ready to provide or accept data and is always an output. HOLD is always an input and is asserted by the host if it cannot accept/provide data. For example, JDATA mode allows ...
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... ADV212 INTERNAL REGISTERS This section describes the internal registers of the ADV212. DIRECT REGISTERS The ADV212 has 16 direct registers, as listed in Table 18. The direct registers are accessed over the ADDR [3:0], HDATA [31:0 and ACK pins. Table 18. Direct Registers Address Name 0x00 PIXEL 0x01 ...
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... IADDR and IDATA registers, and the 16-bit hosts use the IADDR, the IDATA, and the stage register. For additional information on accessing and configuring these registers, see the ADV212 User’s Description Pixel/video format Horizontal count Vertical count ...
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... If this delay is not implemented, erratic behavior might result. MCLK is the input clock to the ADV212 PLL and is used to generate the internal JCLK (JPEG 2000 processor clock) and HCLK (embedded CPU clock). ...
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... Hardware Boot Mode 4 CFG<1> tied low, CFG<2> tied high Hardware Boot Mode 6 CFG<1> and CFG<2> tied high Description No boot host mode. ADV212 does not boot, but all internal registers and memory are accessible through normal host input/output operations. Reserved. Reserved. Rev Page ...
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... ADV212 VIDEO INPUT FORMATS The ADV212 supports a wide variety of formats for uncompressed video and still image data. The actual interface and bus modes selected for transferring uncompressed data dictates the allowed size of the input data and the number of samples transferred with each access. ...
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... Table 25. Maximum Supported Tile Width for Data Input on HDATA and VDATA Buses Compression Mode Input Format 9/7i Single-component 9/7i Two-component 9/7i Three-component 5/3i Single-component 5/3i Two-component 5/3i Three-component 5/3r Single-component 5/3r Two-component 5/3r Three-component Tile/Precinct Maximum Width 2048 1024 each 1024 (Y) 4096 2048 (each) 2048 (Y) 4096 2048 1024 Rev Page ADV212 ...
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... ADV212 JPEG 2000 video processor. ENCODE—MULTICHIP MODE Due to the data input rate limitation (see Table 23), an 1080i application requires at least two ADV212s to encode or decode full-resolution 1080i video. In encode mode, the ADV212 accepts Y and CbCr data on separate buses. An encode example is shown in Figure 33. ...
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... IRQ DREQ DACK In a slave/slave configuration, the common HVF for both ADV212s is generated by an external house sync and each SCOMM[5] is connected to the same GPIO output on the host. SWIRQ1, Software Interrupt 1 in the EIRQIE register, must be unmasked on both devices to enable multichip mode. ...
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... DIGITAL STILL CAMERA/CAMCORDER Figure typical configuration for a digital camera or camcorder. AD9843A 10 D[9:0] SDATA SCK SL Figure 35. Digital Still Camera/Camcorder Encode Application for 10-Bit Pixel Data Using Raw Pixel Mode FPGA ADV212 MCLK DATA INPUTS[9:0] VCLK VFRM SERIAL DATA VRDY SERIAL CLK VSTRB SERIAL EN ...
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... ENCODE/DECODE SDTV VIDEO APPLICATION Figure 36 shows two ADV212 chips using a 10-bit CCIR 656 in normal host mode. ENCODE MODE 32-BIT HOST CPU DATA[31:0] ADDR[3:0] DECODE MODE 32-BIT HOST CPU DATA[31:0] ADDR[3:0] ADV212 VDATA[11:2] VCLK HDATA[31:0] 27MHz MCLK INTR IRQ OSC ADDR[3: ...
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... ADV212 32-BIT HOST APPLICATION Figure 37 shows two ADV212 chips using a 10-bit CCIR 656 in normal host mode. FPGA DATA[31:0] 32-BIT HOST CPU DATA[31:0] ADDR[3:0] FPGA DATA[31:0] 31-BIT HOST CPU DATA[31:0] ADDR[3:0] ADV212 DREQ0 DREQ0 DACK0 DACK0 VDATA[11:2] HDATA[31:0] VCLK 27MHz MCLK OSC ...
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... HDATA<2> Cr0/G3<1> HDATA<1> Cr0/G3<0> HDATA<0> DATA<31:0> ACK ACK IRQ IRQ DREQ DREQ0 DACK DACK0 DREQ DREQ1 DACK DACK1 74.25MHz MCLK Figure 38. Host Interface—Pixel Interface Mode Rev Page ADV212 COMPRESSED DATA PATH RAW PIXEL DATA PATH ADV212 ...
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... ADV212 JDATA INTERFACE Figure 39 shows a typical configuration using JDATA with a dedicated JDATA output, 16-bit host, and 10-bit CCIR 656. FPGA 16-BIT HOST CPU DATA[15:0] ADDR[3:0] ADV212 YCrCb JDATA[7:0] VDATA[11:2] HOLD FIELD VALID VSYNC HSYNC VCLK HDATA[15:0] IRQ IRQ ADDR[3:0] 27MHz MCLK ...
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... Figure 41. 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-144-3) Dimensions shown in millimeters Rev Page CORNER INDEX AREA 1.31 1.21 1.11 0.20 COPLANARITY SEATING PLANE A1 CORNER INDEX AREA 1.32 1.21 1.11 COPLANARITY 0.20 MAX SEATING PLANE ADV212 ...
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... Range 1 ADV212BBCZ-115 −40°C to +85°C 1 ADV212BBCZRL-115 −40°C to +85°C 1 ADV212BBCZ-150 −40°C to +85°C 1 ADV212BBCZRL-150 −40°C to +85° Pb-free part. Speed Grade Operating Voltage Package Description 115 MHz 1.5 V Internal, 121-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 2 ...
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... NOTES Rev Page ADV212 ...
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... ADV212 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06389-0-10/06(0) Rev Page ...