dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 70

• Manufacturer Part Number: dp8344b
• Description: Biphase Communications Processor?bcp
• Manufacturer: National Semiconductor Corporation

4 0 Remote Interface and Arbitration System (RIAS)
The BCP Remote Arbitrator State Machine (RASM) must
know what hardware interfaces to the RP in order to time
the remote accesses correctly To accomplish this three
Interface Mode bits in RIC are used to define the hard-
ware interface These bits are the Latched Write bit LW
the Latched Read bit LR and the Fast Buffered Write bit
All combinations of Remote Reads or Writes with buffers or
latches can be configured via the Interface Mode bits A
Buffered Read is accomplished by using a buffer for block D
and setting LR
and setting LR
Reads Using buffers for blocks A B and C and setting
ting FBW
FBW See Figure 4-13
LW
BIS
7
e
0 allows either a Slow or Fast Buffered Write Set-
SS
e
6
FIGURE 4-13 Interface Mode Bits
0 configures RASM for a Slow Buffered Write
X
Interface Mode Bits
0 – 0 - Slow Buffered Write
1 – 0 - Fast Buffered Write
X – 1 - Latched Write
– 0 – - Buffered Read
– 1 – - Latched Read
FBW
e
e
5
0 Conversely using a latch for block D
1 configures the RASM for Latched
LR
4
LW
3
FIGURE 4-12 Minimum BCP Remote Processor Interface
Y
ST
2
MS1
1
MS0
0
70
and FBW
Latched Write is accomplished by using latches for blocks
A B and C and setting LW
4 1 4 Execution Control
The BCP can be started and stopped in two ways If the
BCP is not interfaced to another processor it can be started
by pulsing RESET low while both REM-RD and REM-WR
are low Execution then begins at location zero If there is a
Remote Processor interfaced to the BCP a write to RIC
which sets the start bit STRT high will begin execution at
the current PC location Writing a zero to STRT stops exe-
cution after the current instruction is completed A Single-
Step is accomplished by writing a one to the Single-Step bit
PC increment the PC and then return to idle SS returns
low after the single-stepped instruction has completed SS
is a write only bit and will always appear low when RIC is
read
Two pins (WAIT and LOCK) and one register bit
can also affect the BCP CPU or RIAS execution The WAIT
pin can be used to add wait states to a remote access
When WAIT must be asserted low to add wait states is de-
pendent on which remote access mode is being used The
information needed to calculate when WAIT must be assert-
ed to add wait states is contained within the individual de-
scriptions of the modes in the next section (4 2 RIAS Func-
tional Description)
SS in RIC This will execute the instruction at the current
e
1 designates a Fast Buffered Write A
(Continued)
e
1
TL F 9336 – 96
LOR