dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 120
dp8344b
Manufacturer Part Number
dp8344b
Description
Biphase Communications Processor?bcp
Manufacturer
National Semiconductor Corporation
Datasheet
1.DP8344B.pdf
(184 pages)
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5 0 Device Specifications
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note 1 All parameters are individually tested and guaranteed Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results
Note 2 Two remote writes to instruction memory are necessary to store a 16-bit instruction word to IMEM low byte followed by high byte The timing of the 2nd
write is shown in the following diagram The timing of the first write is the same as a write of the PC or RIC as shown in Figure 5-20
SU-RRW-CO
H-RRW-X
SU-CMD-RRW
H-CMD-RRW
PD-RRW-X
PD-Xf-LCLr
PD-LCL-X
PD-Xr-LCLf
AZ-AAD-LCL
ZA-LCL-AAD
PD-RDAT-I
H-RDAT-X
PD-IWR-X
PD-LCL-IA
PD-LCL-IWR
PD-X-IWR
ZA-IWR-I
AZ-IWR-I
PD-I-IWR
W-IWR
PD-I-IA
Symbol
ID
10
11
12
13
14
15
16
17
18
19
20
21
1
2
3
4
5
6
7
8
9
RAE REM-WR Falling before CLK-OUT Rising
RAE REM-WR Rising after XACK Rising
CMD Valid before RAE REM-WR Falling
CMD Invalid after RAE REM-WR Falling
RAE REM-WR Falling to XACK Falling
XACK Falling to LCL Rising
LCL Rising to XACK Rising
XACK Rising to LCL Falling
A AD Disabled before LCL Rising
A AD Enabled after LCL Falling
AD (Data) Valid to I Valid
AD (Data) Invalid after XACK Rising
IWR Falling before XACK Rising
LCL Falling to next IA Valid
LCL Rising to IWR Falling
XACK Rising to IWR Rising
IWR Falling to I Enabled
IWR Rising to I Disabled
I Valid before IWR Rising
IWR Low Time
I Disabled to IA Invalid
TABLE 5-22 Fast Buffered Write of IMEM (Notes 1 2)
(Continued)
Parameter
120
(n
(n
(n
(n
2T
Formula
T
IW
IW
IW
IW
a
T
T
a
T
T
a
T
a
T
a
a
H
L
T
a
a
a
a
T
a
a
2)T
2)T
1)T
2)T
H
H
a
a
a
a
a
a
b
b
b
b
b
b
b
b
b
Min
b
b
b
b
24
26
22
0
0
3
10
11
20
10
19
19
18
10
70
5
3
2
2
Max
26
11
30
52
8
5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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