dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 56

• Manufacturer Part Number: dp8344b
• Description: Biphase Communications Processor?bcp
• Manufacturer: National Semiconductor Corporation

3 0 Transceiver
lates odd parity on the data byte (B2 – B9) and transmits this
value for B10 If TCR 2
parity calculated on B1 – B11 and transmitted as B12 the
frame delimiter If OWP is high odd parity is output other-
wise even parity is transmitted In this manner the system
designer is provided with maximum flexibility in defining the
transmitted 3270 control bits (B10 – B12)
When data is written to RTR
TCR 0
TCR are loaded into the FIFO along with the data being
Odd Word Parity OWP controls the type of
(Continued)
is high B10 takes the state of
FIGURE 3-9 3270 3299 Frame Assembly Disassembly Procedure
the least significant 4 bits of
(a) 3270 Data and Command Frames
(b) 3299 Address Frame
56
written to RTR
be used for more than one frame of a multi-frame transmis-
sion or changed for each frame
When a 3270 frame is received and decoded the decoder
loads the parallel data into the receive FIFO where it propa-
gates through to the last location and is mapped into RTR
and TSR
ty BP is odd parity on B2 – B9 calculated in the decoder
Reading RTR will advance the receive FIFO therefore
TSR must be read first if this information is to be utilized
Bits B2 – B11 are exactly as received Byte Pari-
The same TCR contents can therefore
TL F 9336 – 48
TL F 9336 – 47