dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 180

• Manufacturer Part Number: dp8344b
• Description: Biphase Communications Processor?bcp
• Manufacturer: National Semiconductor Corporation

6 0 Reference Section
Scope are single PC expansion cards that can record de-
code and display activity on the 3270 coax and 5250 twinax
line respectively These devices also allow the play back of
the recorded controller information Capstone Technology
also supplies a line monitor The CT101C Network Analysis
Monitor (NAM) is a coax line monitor
These companies can be contacted at the following loca-
tions
For technical assistance in using the DP8344B contact the
BCP Hot Line [phone]
6 6 DP8344A AND DP8344B COMPATIBILITY GUIDE
The DP8344B is an enhanced version of the DP8344A ex-
hibiting improved switching performance and additional
functionality The device has been characterized in a num-
ber of applications and found to be a compatible replace-
ment for the DP8344A Differences between the DP8344A
and DP8344B are detailed in this section
6 6 1 Timing Changes to the CPU
Relative to the DP8344A the DP8344B incorporates a num-
ber of timing changes designed to improve the system inter-
face These timing changes are improvements in the timing
specifications and therefore should allow the DP8344B to
drop into existing DP8344A designs without any hardware
modifications
Note No
AN-623
AN-624
AN-516
AN-504
AN-499
AN-625
AN-627
AN-626
AN-641
AN-688
Azure Technology Inc
38 Pond Street
Franklin Massachusettes 02038
[phone]
Capstone Technology
853 Brown Rd Suite 207
Fremont California 94539
[phone]
New Leaf Technology Ltd
24A High Street
Cobham
Surrey
KT113EB
ENGLAND
(0932) 66466
App
TABLE 6-4 DP8344 Application Notes
Interfacing Memory to the DP8344B
A Combined Coax-Twisted Pair 3270 Line
Interface for the DP8344 Biphase
Communications Processor
Interfacing the DP8344 to Twinax
DP8344 BCP Stand-Alone Soft-Load
System
‘‘Interrupts’’-A Powerful Tool of the Biphase
Communications Processor
JRMK Speeds Command Decoding
DP8344 Remote Processor Interfacing
DP8344 Timer Application
MPA - A Multi-Protocol Terminal Emulation
Adapter Using the DP8344
The DP8344 BCP Inverse Assembler
Title
(Continued)
180
The DP8344A exhibits a small amount of contention be-
tween certain bus signals as detailed in the Device Specifi-
cations section of this data sheet The DP8344B interface
timing improvements are designed to reduce and or elimi-
nate this bus contention
6 6 2 Additional Functionality of the DP8344B
6 6 2 1 4 T-state Read
To eliminate bus contention during memory accesses a
new optional read mode has been created controlled by








70 ns Data Memory
At a 20 MHz CPU clock rate the DP8344B can support 70
ns static RAM for data memory with no wait states The
DP8344A was limited to 55 ns static RAM for data memo-
ry with no wait states (See Section 5 0 Device Specifica-
tions )
READ
The timing of the READ strobe has been improved to re-
duce bus contention during a data memory access There
is now more time between AD disabled and READ falling
as well as one-half T-state between READ rising and AD
enabled In addition a new 4 T-state read option has been
provided to eliminate bus contention (See Section 5 0 De-
vice Specifications for timing changes and 4 T-state
Read later in this document for more information on the 4
T-state Read option )
The user can therefore choose between a fast read mode
(3 T-states) with a small amount of contention and a slow-
er read mode (4 T-states) with no contention
A AD Bus Timing
The timing of the A and AD buses has been changed to
eliminate bus contention during remote accesses of data
memory There is now a one-half T-state TRI-STATE zone
during the bus transfer from local to remote control and
vice versa (See Section 5 0 Device Specifications )
IWR
The timing of IWR has been changed such that IWR now
falls one T-state earlier This eliminates bus contention
during the start of soft loads (See Section 5 0 Device
Specifications )
IA Bus Softload Timing
The auto-increment of the IA bus address during soft
loads of instruction memory now occurs one T-state later
to maintain in-phase data and thereby eliminate bus con-
tention (See Seection 5 0 Device Specifications )
LCL
LCL is now removed when REM-RD is taken high on buff-
ered reads of RIC
memory to eliminate bus contention in this mode (See
Section 5 0 Device Specifications )
RIC
The hold time on slow buffered writes to RIC and the
program counter has been improved (See Section 5 0 De-
vice Specifications )
‘‘Kick-start’’
The hold time on REM-WR and REM-RD to RESET to
‘‘kick-start’’ the CPU has been improved (See Section 5 0
Device Specifications )
the program counter and instruction