dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 44

• Manufacturer Part Number: dp8344b
• Description: Biphase Communications Processor?bcp
• Manufacturer: National Semiconductor Corporation

2 0 CPU Description
Internal
The internal interrupts consist of the Transmitter FIFO Emp-
ty TFE interrupt the Line Turn Around LTA interrupt the
Time Out TO interrupt and a user selectable receiver inter-
rupt source The receiver interrupt source is selected from
either the Receiver FIFO Full RFF interrupt the Data
Available DA interrupt or the Receiver Active RA inter-
rupt The receiver interrupt is selected using bits RIS1 and
Section 3 0 Transceiver for a description of these inter-
rupts
Masking
The BCP uses two levels of interrupt masking a global inter-
rupt mask which affects all interrupts except NMI and indi-
vidual interrupt mask bits Global enabling and disabling of
the interrupts is performed by changing the state of the
Global Interrupt Enable bit GIE in ACR
interrupts are disabled when GIE is a zero and enabled
when GIE is a one GIE is a zero after the BCP is reset
using any instruction that can write to ACR
the RET RETF and EXX instructions have option fields
which can be used to alter the state of GIE
instruction can set or clear GIE as well as leaving it un-
changed The RET and RETF instructions can restore GIE
to the value that was saved on the address stack at the time
the interrupt was recognized These instructions also pro-
RIS0 in the Interrupt Control Register
GIE is a read write register bit and may be changed by
(Continued)
NMI
RFF DA RA
TFE
LTA
BIRQ
TO
Interrupt
TABLE 2-27 ICR Interrupt Mask Bits
ICR
The maskable
In addition
The EXX
See the
and Interrupt Priority
Mask Bit
44
IMO
IM1
IM2
IM3
IM4
vide the options of clearing or setting GIE or leaving it
unchanged GIE is set to a zero when an interrupt is rec-
ognized by the CPU It is necessary to set GIE to a one if
interrupts are to be recognized within an interrupt routine
The individual interrupt mask bits are located in
When set to a one bits IM0
in ICR mask the receiver interrupt TFE interrupt LTA in-
terrupt BIRQ interrupt and TO interrupt respectively To
enable an interrupt its mask bit must be set to a zero The
interrupts and associated mask bits are shown in
Table 2-27 These bits are set to a one when the DP8344 is
reset
Masking interrupts with GIE or the mask bits in ICR pre-
vents the CPU from acknowledging interrupts but does not
prevent the interrupts from occurring Therefore if an inter-
rupt is asserted it will be processed as soon as it is un-
masked by changing GIE to a one and or changing the
appropriate mask bit in ICR to a zero
Priorites
When more than one interrupt is unmasked and asserted
the CPU processes the interrupt with the highest priority
first NMI has the highest priority followed by the receiver
interrupt TFE LTA BIRQ and TO Each time the interrupts
are sampled the highest priority interrupt is processed first
regardless of how long a lower priority interrupt has been
active Interrupt priority is summarized in Table 2-27
Priority
Highest
Lowest
IM1
IM2
IM3 and IM4
ICR