dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 62

• Manufacturer Part Number: dp8344b
• Description: Biphase Communications Processor?bcp
• Manufacturer: National Semiconductor Corporation

4 0 Remote Interface and Arbitration System (RIAS)
INTRODUCTION
Communication with the BCP is based on the BCP’s ability
to share its data memory A microprocessor (or any intelli-
gent device) can read and write to any BCP data location
while the BCP CPU is executing instructions This capability
is part of the BCP’s Remote Interface and Arbitration Sys-
tem (RIAS) Sharing data memory is possible because
RIAS’s arbitration logic allocates use of the BCP’s data and
address buses RIAS has been designed so that accesses
of BCP data memory by another device minimally impact its
performance as well as the BCP’s In addition to data mem-
ory accesses RIAS allows another device to control how
BCP programs are loaded started and debugged
4 1 RIAS ARCHITECTURAL DESCRIPTION
Interfacing to the BCP is accomplished with the control sig-
nals listed in Table 4-1 Figure 4-1 shows the BCP inter-
faced to Instruction Memory Data Memory and an intelli-
gent device termed the Remote Processor (RP) Instruction
and Data are separate memory systems with separate ad-
dress buses and data paths This arrangement allows con-
tinuous instruction fetches without interleaved data access-
es Instruction Memory (IMEM) is interfaced to the BCP
through the Instruction (I) and Instruction Address (IA) bus-
es IMEM is 16 bits wide and can address up to 64k memo-
ry Data Memory (DMEM) is eight bits wide and can also
address up to 64k memory The DMEM address is formed
by the 8-bit upper byte (A bus) and the 8-bit lower byte (AD
bus) The AD bus must be externally latched because it also
serves as the path for data between the BCP and DMEM
For further information on how AD bus is used refer to Sec-
tion 2 2 2 CPU Timing
The Remote Processor’s address and data buses are con-
nected to the BCP’s address and data buses through the
FIGURE 4-1 BCP Remote Processor Interface
62
bus control circuitry The RP’s address lines decode a chip
select for the BCP called Remote Access Enable (RAE)
Basically the BCP’s Data Memory has been memory
mapped into the RP’s memory A Remote Access of the
BCP occurs when REM-RD or REM-WR along with RAE is
asserted low REM-RD and REM-WR can be directly con-
nected to the Remote Processor’s read and write lines or
for more complicated systems the REM-RD and REM-WR
signals may be controlled by a combination of address de-
code and the RP’s read and write signals To the RP an
access of the BCP will appear as any other memory system
access This configuration allows the RP to read and write
Data Memory read and write the BCP’s Program Counter
and read and write BCP Instruction Memory These func-
tions are selected by control bits in the Remote Interface
Configuration register RIC
only by the RP and not by the BCP CPU If the Remote
Processor executes a remote access with the Command
input (CMD) high
bus
In Figure 4-1 the Remote Processor’s address lines are
decoded to form the CMD input When a remote access
takes place with CMD low the memory system designated
in RIC is accessed Figure 4-2 shows the contents of
bits MS1 – 0 which designate the type of remote access to
Data Memory the Program Counter or Instruction Memory
This register also contains the BCP start bit STRT three
interface select bits FBW LR LW
to the RIAS Reference Section for a more detailed descrip-
tion of the contents of this register and the function of each
bit
SS and the Bi-directional Interrupt Status bit BIS Refer
RIC
The two least significant bits are the Memory Select
RIC is accessed through the BCP’s AD
This register can be accessed
TL F 9336 – 19
the Single-Step bit