mpc8555e Freescale Semiconductor, Inc, mpc8555e Datasheet - Page 67

• Manufacturer Part Number: mpc8555e
• Description: Mpc8555e Powerquicc Iii Processor With Integrated Security
• Manufacturer: Freescale Semiconductor, Inc

15.2
The platform clock is the clock that drives the L2 cache, the DDR SDRAM data rate, and the e500 core
complex bus (CCB), and is also called the CCB clock. The values are determined by the binary value on
LA[28:31] at power up, as shown in
There is no default for this PLL ratio; these signals must be pulled to the desired values.
For specifications on the PCI_CLK, refer to the PCI 2.2 Specification.
Freescale Semiconductor
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Platform/System PLL Ratio
LA[28:31] Signals
Binary Value of
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table
Table 46. CCB Clock Ratio
46.
16:1 ratio CCB clock: SYSCLK (PCI bus)
Reserved
2:1 ratio CCB clock: SYSCLK (PCI bus)
3:1 ratio CCB clock: SYSCLK (PCI bus)
4:1 ratio CCB clock: SYSCLK (PCI bus)
5:1 ratio CCB clock: SYSCLK (PCI bus)
6:1 ratio CCB clock: SYSCLK (PCI bus)
Reserved
8:1 ratio CCB clock: SYSCLK (PCI bus)
9:1 ratio CCB clock: SYSCLK (PCI bus)
10:1 ratio CCB clock: SYSCLK (PCI bus)
Reserved
12:1 ratio CCB clock: SYSCLK (PCI bus)
Reserved
Reserved
Reserved
Ratio Description
Clocking
67