mpc8555e Freescale Semiconductor, Inc, mpc8555e Datasheet - Page 3

• Manufacturer Part Number: mpc8555e
• Description: Mpc8555e Powerquicc Iii Processor With Integrated Security
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
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Security Engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
IEEE Std 802.11i™, iSCSI, and IKE processing. The Security Engine contains 4 Crypto-channels,
a Controller, and a set of crypto Execution Units (EUs). The Execution Units are:
— Public Key Execution Unit (PKEU) supporting the following:
— Data Encryption Standard Execution Unit (DEU)
— Advanced Encryption Standard Unit (AESU)
— ARC Four execution unit (AFEU)
— Message Digest Execution Unit (MDEU)
— Random Number Generator (RNG)
— 4 Crypto-channels, each supporting multi-command descriptor chains
High-performance RISC CPM operating at up to 333 MHz
— CPM software compatibility with previous PowerQUICC families
— One instruction per clock
— Executes code from internal ROM or instruction RAM
— 32-bit RISC architecture
— Tuned for communication environments: instruction set supports CRC computation and bit
— Internal timer
— Interfaces with the embedded e500 core processor through a 32-Kbyte dual-port RAM and
— Handles serial protocols and virtual DMA
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
– RSA and Diffie-Hellman
– Programmable field size up to 2048-bits
– Elliptic curve cryptography
– F2m and F(p) modes
– Programmable field size up to 511-bits
– DES, 3DES
– Two key (K1, K2) or Three Key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
– Implements the Rinjdael symmetric key cipher
– Key lengths of 128, 192, and 256 bits.Two key
– ECB, CBC, CCM, and Counter modes
– Implements a stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
– SHA with 160-bit or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
– Static and/or dynamic assignment of crypto-execution units via an integrated controller
– Buffer size of 256 Bytes for each execution unit, with flow control for large data sizes
manipulation.
virtual DMA channels for each peripheral controller
Overview
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