mpc8560vt667jb Freescale Semiconductor, Inc, mpc8560vt667jb Datasheet - Page 92

• Manufacturer Part Number: mpc8560vt667jb
• Description: Mpc8560 Powerquicc Iii Integrated Communications Processor
• Manufacturer: Freescale Semiconductor, Inc

System Design Information
17 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8560.
17.1 System Clocking
The MPC8560 includes three PLLs.
17.2 PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AV
AV
these voltages will be derived directly from V
following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide three independent filter circuits as illustrated in
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
pin, which is on the periphery of the 783 FC-PBGA footprint, without the inductance of vias.
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DD
1. The platform PLL generates the platform clock from the externally supplied SYSCLK input. The
2. The e500 Core PLL generates the core clock as a slave to the platform clock. The frequency ratio
3. The CPM PLL is slaved to the platform clock and is used to generate clocks used internally by the
2, and AV
frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio
configuration bits as described in
between the e500 core clock and the platform clock is selected using the e500 PLL ratio
configuration bits as described in
CPM block. The ratio between the CPM PLL and the platform clock is fixed and not under user
control.
DD
3, respectively). The AV
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Section 15.2, “Platform/System PLL Ratio.”
Section 15.3, “e500 Core PLL Ratio.”
DD
DD
level should always be equivalent to V
through a low frequency filter scheme such as the
Figure
58, one to each of the three AV
DD
pin being supplied to minimize
Freescale Semiconductor
DD
, and preferably
DD
pins. By
DD
1,
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