mpc8560vt667jb Freescale Semiconductor, Inc, mpc8560vt667jb Datasheet - Page 64

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mpc8560vt667jb

Manufacturer Part Number
mpc8560vt667jb
Description
Mpc8560 Powerquicc Iii Integrated Communications Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
RapidIO
The compliance of driver output signals TD[0:15] and TFRAME with their minimum data valid window
(DV) specification shall be determined by generating an eye pattern for each of the data signals and
comparing the eye pattern of each data signal with the RapidIO transmit mask shown in
value of X2 used to construct the mask shall be (1 – DV
window specification if the transmit mask can be positioned on the signal’s eye pattern such that the eye
pattern falls entirely within the unshaded portion of the mask.
64
Differential output high voltage
Differential output low voltage
Duty cycle
V
differential signal swing
V
differential signal swing
Data valid
Skew of any two data outputs
Skew of single data outputs to associated clock
Notes:
1.See
2.Requires ±100 ppm long term frequency stability.
3.Measured at V
4.Measured using the RapidIO transmit mask shown in
5.See
6.Guaranteed by design.
OD
OD
rise time, 20%–80% of peak to peak
fall time, 20%–80% of peak to peak
Figure
Figure
44.
49.
Table 50. RapidIO Driver AC Timing Specifications—1 Gbps Data Rate
OD
Characteristic
= 0 V.
V
V
V
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
V
OHDmax
OLDmax
OHDmin
OLDmin
0
0
Figure 44. RapidIO Transmit Mask
X2
t
SKEW,PAIR
Symbol
t
V
V
Figure
t
t
DPAIR
FALL
RISE
DC
DV
OHD
OLD
Time (UI)
44.
min
DV
)/2. A signal is compliant with the data valid
–540
–100
Min
200
100
100
575
48
1–X2
Range
–200
Max
540
100
100
52
1
Freescale Semiconductor
Unit
mV
mV
ps
ps
ps
ps
ps
%
Figure
Notes
2, 6
3, 6
4, 6
5, 6
44. The
1
1
6
6

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